
W39L040A
Publication Release Date: April 14, 2005
- 9 -
Revision A3
6.4.2
The W39L040A also features the "Toggle Bit" as a method to indicate to the host system that the
embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling)
data from the device at any address will result in DQ6 toggling between one and zero. Once the
Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will
be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising
edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid
after the rising edge of the sixth #WE pulse in the six write pulse sequence. For sector erase, the
Toggle Bit is valid after the last rising edge of the sector erase #WE pulse. The Toggle Bit is active
during the sector erase time-out.
Either #CE or #OE toggling will cause DQ6 to toggle.
DQ6: Toggle Bit
6.5 Table of Operating Modes
6.5.1
Device Bus Operations
(V
ID
= 12
±
0.5V)
PIN
MODE
#CE #OE #WE
V
IL
V
IL
V
IL
V
IH
V
IH
X
V
IL
A0
A0
A0
X
X
X
X
V
IL
V
IH
A1
A1
A1
X
X
X
X
V
IL
V
IL
A9
A9
A9
X
X
X
X
V
ID
V
ID
DQ0
DQ7
Dout
Din
High Z
High Z/
Dout
High Z/
Dout
High Z
Code
Code
Read
Write
Standby
V
IH
V
IL
X
X
X
Write Inhibit
X
V
IL
V
IL
V
IL
X
V
IH
V
IH
V
IH
V
IH
Output Disable
Auto select Manufacturers ID
Auto select Device ID
V
IH
V
IL
V
IL
6.5.2
Auto-select Codes (High Voltage Method)
(V
ID
= 12
±
0.5V)
DESCRIPTION
#CE #OE
#WE
A9
THE OTHER ADDRESS
DQ[7:0]
Manufacturer ID: Winbond
V
IL
V
IL
V
IH
V
ID
All Address = V
IL
DAhex
Device ID: W39L040A
V
IL
V
IL
V
IH
V
ID
A1 = V
IH
, All other = V
IL
D6hex