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參數資料
| 型號： | W530-02HT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Frequency-multiplying, Peak-reducing EMI Solution |
| 中文描述： | 166 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件頁數： | 5/8頁 |
| 文件大小： | 92K |
| 代理商： | W530-02HT |
W530-02
Document #: 38-07190 Rev. *A
Page 5 of 8
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
Parameter
V
DD
, V
IN
Voltage on any Pin with Respect to GND
T
STG
Storage Temperature
T
A
Operating Temperature
T
B
Ambient Temperature under Bias
P
D
Power Dissipation
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Rating
–
0.5 to +7.0
–
65 to +150
0 to +70
–
55 to +125
0.5
Description
Unit
V
°
C
°
C
°
C
W
DC Electrical Characteristics
:
0
°
C < T
A
< 70
°
C, V
DD
= 3.3V ±0.3V
Parameter
Description
I
DD
Supply Current
t
ON
Power-Up Time
Test Condition
Min.
Typ.
18
Max.
32
5
Unit
mA
ms
First locked clock cycle after Power
Good
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
OL
I
OH
C
I
R
P
Z
OUT
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
0.8
V
V
V
V
μ
A
μ
A
mA
mA
pF
k
2.4
0.4
2.4
Note 2
Note 2
@ 0.4V, V
DD
= 3.3V
@ 2.4V, V
DD
= 3.3V
–
100
10
15
15
7
80
25
DC Electrical Characteristics:
0
°
C < T
A
< 70
°
C, V
DD
= 5V ±10%
Parameter
Description
I
DD
Supply Current
t
ON
Power-Up Time
Test Condition
Min.
Typ.
30
Max.
50
5
Unit
mA
ms
First locked clock cycle after
Power Good
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
OL
I
OH
C
I
R
P
Z
OUT
Note:
2.
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
0.15V
DD
V
V
V
V
μ
A
μ
A
mA
mA
pF
k
0.7V
DD
0.4
2.4
Note 2
Note 2
@ 0.4V, V
DD
= 5V
@ 2.4V, V
DD
= 5V
–
100
10
24
24
7
80
25
Inputs OR1:2 and IR1:2 have a pull-up resistor, Input SSON# has a pull-down resistor.
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