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參數(shù)資料
型號(hào): W53320
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 16Voice/Melody/LCD Controller(View TalkTM Series)
中文描述: 4-BIT, MROM, MICROCONTROLLER, XSS
封裝: COB
文件頁數(shù): 4/9頁
文件大小: 61K
代理商: W53320
W53300/W53320
- 4 -
PIN DESCRIPTION
SYMBOL
XIN
I/O
I
FUNCTION
Input pin for oscillator. It can be connected to crystal, or can connect a
resistor to VDD to generate main system clock. Oscillator can be
stopped when SCR.1 is set to logic 1.
Output pin for oscillator which is connected to another crystal pin.
32.768 KHz crystal input pin.
32.768 KHz crystal output pin.
General Input/Output port specified by PM1 register. If output mode is
selected, PM0 register can be used to specify CMOS/NMOS driving
capability option. Initial state is input mode.
XOUT
X32I
O
I
X32O
RA0 ~ RA3
O
I/O
RB0 ~ RB3
I/O
General Input/Output port specified by PM2 register. If output mode is
selected, PM0 register can be used to specify CMOS/NMOS driving
capability option. Initial state is input mode.
4-bit schmitt input with internal pull high option specified by PM0
register. RC0 can be used as clock source for Timer 1. Each pin has
an independent interrupt capability specified by PEFL special register.
4-bit schmitt input port with internal pull high option specified by PM0
register. Each pin has an independent interrupt capability specified by
PEFH special register.
Output port only. RE3 may use as TONE if bit 0 of MR0 special
register is set to logic 1.
System reset pin with internal pull-high resistor is active low.
Test pin. No connect for normal use.
Connects resistor to VDD to generate speech or melody clock source.
Power source for PWM output.
Synchronous LED1 output while speech play/melody is active.
Synchronous LED2 output only while speech play is active.
Speaker direct driving output 1 while speech or melody is active.
Speaker direct driving output 2 while speech or melody is active.
LCD segment output pins.
LCD common signal output pins. The LCD alternating frequency is
fixed at 64Hz. COM16~31 are useless for W53300.
Connection terminals for voltage doubler capacitor.
Connects a 1uF capacitor to VSS1 to double VDD voltage output if
triple pump option is enabled. Otherwise, VDD2 connects to VDD
directly if double pump option is enabled.
An output if internal pump circuit is enabled. It connects a 1uF
capacitor to VSS. Triple VDD voltage will be output if triple pump
option is enabled. Otherwise, double VDD voltage will be output if
double pump option is enabled.
An input if internal pump voltage is disabled.
RC0 ~ RC3
I
RD0 ~ RD3
I
RE0~RE3/TONE
O
RES
TEST
ROSC
I
I
I
VDDP
LED1
LED2
PWM1
PWM2
SEG0
SEG47
COM0
COM31
I
O
O
O
O
O
O
DH1, DH2
VDD2
I
O
VDD3
O/I
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