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參數資料
| 型號： | W541L260 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT MICROCONTROLLER |
| 中文描述： | 4-BIT, OTPROM, 1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數： | 6/11頁 |
| 文件大小： | 129K |
| 代理商： | W541L260 |
W541L260
- 6 -
5. PIN DESCRIPTION
SYMBOL
I/O
FUNCTION
XIN1
I
Input pin for oscillator.
Connected to crystal or resistor to generate system clock by code option.
External 10~20pF capacitor uses to get accurate freq in crystal mode.
Output pin for oscillator.
Connected to crystal or resistor to generate system clock by code option.
20pF capacitor is built in internal for crystal mode.
Input pin for sub-oscillator. Connected to a 32.768 KHz crystal. External
10~20pF capacitor uses to get accurate freq in crystal mode.
Output pin for sub-oscillator. Connected to a 32.768 KHz crystal. 20pF
capacitor is built in internal for crystal mode.
Input/Output port.
Input/output mode specified by port mode 1 register (PM1).
Input/Output port.
Input/output mode specified by port mode 2 register (PM2).
4-bit port for input only.
Each pin has an independent interrupt capability
.
And build-in schmitt
trigger.
4-bit port for input only.
O This port provides high sink current to drive LEDs.
Output pin only.
This pin can output modulating or nonmodulating frequency, or Timer 1
clock output specified by mode register 1 (MR1).
I
System reset pin with pull-high resistor.
LCD segment output pins.
Can also be used as DC output ports specified by code option.
XOUT1
O
XIN2
I
XOUT2
O
RA0
RA3
I/O
RB0
RB3
I/O
RC0
RC3
I
RD0
RD3
I
RE0
RE3
MFP
O
RES
SEG0
SEG31
O
COM0
COM3
O
LCD common signal output pins.
Static
COM0
COM1
COM2
COM3
Used
Not Used
1/2 Duty
Not Used
Not Used
Not Used
Not Used
1/3 Duty
Not Used
1/4 Duty
Used
Used
Used
Used
Used
Used
Used
Used
Used
The LCD alternating frequency can be selected by code option.
Connection terminals for voltage doubler (halver) capacitor.
Positive (+) supply voltage terminal.
Refer to Functional Description.
Positive power supply (+).
Negative power supply (-).
DH1, DH2
I
V
DD1
, V
DD2
V
DD3
I
V
DD
V
SS
I
I
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