
The Western Design Center, Inc.
W65C02S Datasheet
The Western Design Center, Inc. W65C02S Datasheet
30
Operation
# Immediate Data
~ NOT
^
AND
v
OR
v
Exclusive OR
Processor Status Register (P)
*User Defined
a
(
a
a
(
A
#
i
r
s
z
(
z
z
(
(
7
N
N
.
.
6
V
.
.
.
5
1
.
.
.
4
1
.
.
.
3
D
.
.
.
2
I
.
.
.
1
Z
Z
.
.
0
C
.
.
.
M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ORA
PHA
PHP
PHX
PHY
PLA
PLP
PLX
PLY
RMB0
RMB1
RMB2
RMB3
RMB4
RMB5
RMB6
RMB7
ROL
A V M
→
A
A
→
Ms, S-1
→
S
0D
1D
19
09
05
01
15
12
11
48
P
→
Ms, S-1
→
S
08
X
→
Ms, S-1
→
S
DA
.
.
.
.
.
.
.
.
Y
→
Ms, S-1
→
S
5A
.
.
.
.
.
.
.
.
S + 1
→
S, Ms
→
A
S + 1
→
S, Ms
→
P
68
N
.
.
.
.
.
Z
.
28
N
V
.
1
D
I
Z
C
S + 1
→
S, Ms
→
X
FA
N
.
.
.
.
.
Z
.
S + 1
→
S, Ms
→
Y
7A
N
.
.
.
.
.
Z
.
Reset Memory Bit 0
.
.
.
.
.
.
.
.
Reset Memory Bit 1
.
.
.
.
.
.
.
.
Reset Memory Bit 2
.
.
.
.
.
.
.
.
Reset Memory Bit 3
.
.
.
.
.
.
.
.
Reset Memory Bit 4
.
.
.
.
.
.
.
.
Reset Memory Bit 5
.
.
.
.
.
.
.
.
Reset Memory Bit 6
.
.
.
.
.
.
.
.
Reset Memory Bit 7
.
.
.
.
.
.
.
C
←
7 6 5 4 3 2 1 0
←
C
2E
3E
2A
26
36
N
.
.
.
.
.
Z
C
ROR
RTI
RTS
SBC
SEC
SED
C
→
7 6 5 4 3 2 1 0
→
C
6E
7E
6A
66
76
N
.
.
.
.
.
Z
C
Return from Interrupt
40
N
V
.
1.
D
I
Z
C
Return from Subroutine
60
.
.
.
.
.
.
.
.
A - M - (~C)
→
A
ED
FD
F9
E9
E5
E1
F5
F2
F1
N
V
.
.
.
.
Z
C
1
→
C
38
.
.
.
.
.
.
.
1
1
→
D
F8
.
.
.
.
1
.
.
.