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參數資料
| 型號： | W65C02SPL-14 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數： | 39/40頁 |
| 文件大小： | 1011K |
| 代理商： | W65C02SPL-14 |
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The Western Design Center, Inc.
W65C02S Datasheet
The Western Design Center, Inc. W65C02S Datasheet 39
9
HARD CORE MODEL
9.1
Features of the W65C02S Hard Core Model
The W65C02S core uses the same instruction set as the W65C02S.
The only functional difference between the W65C02S and W65C02S core is the RDY pin. The W65C02S RDY pin is
bi-directional utilizing an active pull-up. The W65C02S core RDY function is split into 2 pins, RDY, WAITN and
WAITP. The WAITN output goes low and WAITP goes high when a WAI instruction is executed.
The ESD and latch-up buffers have been removed.
The output from the core is the buffer N-channel and the P-channel transistor drivers.
The following inputs, if not used, must be pulled to the high state: RDY, IRQB, NMIB, BE and SOB.
The timing of the W65C02S core is the same as the W65C02S.
10
SOFT CORE RTL MODEL
10.1
W65C02 Synthesizable RTL-Code in Verilog HDL
The RTL-Code (
R
egister
T
ransfer
L
evel) in Verilog is a synthesizable model. The behavior of this model is equivalent to
the original W65C02S hardcore. The W65C02 RTL-Code is available as the core model and the W65C02S standard chip
model.
The
standard
chip
model
includes
the
soft-core
and
the
buffer
ring
in
RTL-Code.
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