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參數資料
| 型號： | W6662CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | CCD(Correlated Double Sampler)/CIS(Contact Image Sensors) Analog Front End Signal Processor.(耦合采樣器／接觸圖象傳感器模擬前端信號處理器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 10 X 10 MM, 2 MM HEIGHT, PLASTIC, QFP-48 |
| 文件頁數： | 6/19頁 |
| 文件大?。?/td> | 272K |
| 代理商： | W6662CF |
Preliminary W6662CF
- 6 -
SEL1 = 0, SEL0 = 1 is red channel of gain register and offset register selected.
SEL1 = 1, SEL0 = 0 is green channel of gain register and offset register selected.
SEL1 = 1, SEL0 = 1 is blue channel of gain register and offset register selected.
SEL1 = 0, SEL0 = 0 is reserved.
6.3 CDS vs S&H Mode
"CDS" stands for "correlated double sampling". It is used to reduce noise generated in CCD source
and to decrease the sampling error which induced from clampping voltage error. CDS takes two step
to sample a CCD's output pixel. In the first step, the reset level of CCD output is sampled and hold by
S/H1 at the falling edge of CDSCK1 signal. In the second step, the data signal of CCD output is
sampled and hold by S/H2 at the falling edge of CDSCK2 signal. The CDS output voltage is obtained
from the voltage difference of the outputs of S/H1 and S/H2.
In S&H mode, the data signal of CIS output is sampled and hold by S/H1 at the falling edge of
CDSCK2 signal and the output voltage is obtained from the voltage difference of the outputs of S/H1
and CISREF pin. Figure 6-3 shows the equivalent circuits of CDS and S&H mode processing.
Fig. 6-3 The Equivalent Circuit of CDS and S&H Mode.
S/H1
S/H2
CDSCK1
CDSCK2
+
-
From
I/P
MUX
To
Gain/Offset
Adjust
S/H1
CDSCK2
+
-
From
I/P
MUX
To
Gain/Offset
Adjust
(a) CDS Mode.
(b) S&H Mode.
From
CISREF
pin
6.4 Gain/Offset Adjustment
The analog input signal after CDS or S&H processed is amplified by PGA gain adjustment and then
shifted by offset value. The offset value will not affected by the PGA gain adjustment.
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