
W741L240
Publication Release Date: May 1999
- 13 -
Revision A1
Hold Mode Release Enable Flag (HEF)
The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The
HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I
instruction. The bit descriptions are as follows:
0
1
2
HEF
w
w
w
3
4
5
6
7
Note: W means write only.
HEF.0 = 1 Overflow from Divider 0 causes hold mode to be released.
HEF.1 Reserved
HEF.2 = 1 Signal change at port RC causes hold mode to be released.
HEF.3, 4 Reserved
HEF.5, 6 Reserved
HEF.7 = 1 Underflow from Timer 1 causes hold mode to be released.
Interrupt Enable Flag (IEF)
The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used
to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these
interrupts is accepted, the corresponding bit of the event flag will be reset, but the other bits are
unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I
or
EN INT
is executed again. Besides, these interrupts can be disabled by executing DIS INT instruction.
The bit descriptions are as follows:
0
1
2
IEF
w
w
w
3
4
5
6
7
Note: W means write only.
IEF.0 = 1 Interrupt 0 is accepted by overflow from Divider 0.
IEF.1 Reserved
IEF.2 = 1 Interrupt 2 is accepted by a signal change on port RC.
IEF.3, 4 Reserved
IEF.5, 6 Reserved
IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.