
W741L250
Publication Release Date: March 1998
- 25 -
Revision A2
The relationship between the LCD drive mode and the maximum number of drivable LCD segments
is shown below.
LCD DRIVE MODE
MAX. NUMBER OF
DRIVABLE LCD SEGMENTS
24 (COM1)
48 (COM1
COM2)
72 (COM1
COM3)
72 (COM1
COM3)
96 (COM1
COM4)
CONNECTION AT
POWER INPUT
Connect V
DD3,
V
DD2
to
V
DD1
Connect V
DD3
to V
DD2
Connect V
DD3
to V
DD2
-
-
Static
1/2 bias 1/2 duty
1/2 bias 1/3 duty
1/3 bias 1/3 duty
1/3 bias 1/4 duty
LCD Output Mode Type Flag (LCDM)
The LCD output mode type flag is organized as a 6-bit binary register (LCDM.0 to LCDM.5). These
bits are used to control the LCD output pin architecture. When the LCD output pins are set to DC
output mode by option codes, the architecture of these output pins (segment 0 to segment 23) can be
selected as CMOS or NMOS type by the MOV LCDM, #I instruction. The bit descriptions are as
follows:
w
1
2
3
LCDM
4
w
w
5
0
w
w
w
Note: W means write only.
LCDM.0 = 0 SEG0 to SEG3 work as CMOS output type.
= 1 SEG0 to SEG3 work as NMOS output type.
LCDM.1 = 0 SEG4 to SEG7 work as CMOS output type.
= 1 SEG4 to SEG7 work as NMOS output type.
LCDM.2 = 0 SEG8 to SEG11 work as CMOS output type.
= 1 SEG8 to SEG11 work as NMOS output type.
LCDM.3 = 0 SEG12 to SEG15 work as CMOS output type.
= 1 SEG12 to SEG15 work as NMOS output type.
LCDM.4 = 0 SEG16 to SEG19 work as CMOS output type.
= 1 SEG16 to SEG19 work as NMOS output type.
LCDM.5 = 0 SEG20 to SEG23 work as CMOS output type.
= 1 SEG20 to SEG23 work as NMOS output type.