
W741C240
- 22 -
When Fw = 32.768 KHz, the LCD frequency is as shown in the table below.
LCD FREQUENCY
Fw/512 (64 Hz)
Fw/256 (128 Hz)
Fw/128 (256 Hz)
Fw/64 (512 Hz)
STATIC
64
128
256
512
1/2 DUTY
32
64
128
256
1/3 DUTY
21
43
85
171
1/4 DUTY
16
32
64
128
Corresponding to the 24 LCD drive output pins, there are 24 LCD data RAM segments (LCDR00 to
LCDR17). Instructions such as MOV LCDR, #I; MOV WR, LCDR; MOV LCDR, WR; and MOV LCDR,
ACC are used to control the LCD data RAM. The data in the LCD data RAM are transferred to the
segment output pins automatically without program control. When the bit value of the LCD data RAM
is "1," the LCD is turned on. When the bit value of the LCD data RAM is "0," the LCD is turned off.
The contents of the LCD data RAM (LCDR) are sent out through the segment 0 to segment 23 pins by
a direct memory access. The relationship between the LCD data RAM and segment/common pins is
shown below.
COM3
bit 3
0/1
0/1
.
.
.
0/1
0/1
COM2
bit 2
0/1
0/1
.
.
.
0/1
0/1
COM1
bit 1
0/1
0/1
.
.
.
0/1
0/1
COM0
bit 0
0/1
0/1
.
.
.
0/1
0/1
LCD data RAM
LCDR00
LCDR01
Output pin
SEG0
SEG1
.
.
.
.
.
.
LCDR16
LCDR17
SEG22
SEG23
The LCDON instruction turns the LCD display on (even in HOLD mode), and the LCDOFF instruction
turns the LCD display off. At initial reset, all the LCD segments are lit. When the initial reset state
ends, the LCD display is turned off automatically. To turn on the LCD display, the instruction LCDON
must be executed. The relationship between the LCD drive mode and the maximum number of
drivable LCD segments is shown below.
LCD DRIVE MODE
MAX. NUMBER OF
DRIVABLE LCD SEGMENTS
24 (COM1)
48 (COM1
COM2)
72 (COM1
COM3)
72 (COM1
COM3)
96 (COM1
COM4)
CONNECTION AT
POWER INPUT
Connect V
DD3,
V
DD2
to
V
DD1
Connect V
DD3
to V
DD2
Connect V
DD3
to V
DD2
-
-
Static
1/2 bias 1/2 duty
1/2 bias 1/3 duty
1/3 bias 1/3 duty
1/3 bias 1/4 duty
The output waveforms for the five LCD driving modes are shown below.