
W742S81A
- 12 -
to 0, the clock source of the system clock generator is main-oscillator clock; if the SCR.0 is set to 1, the
clock source of the system clock generator is sub-oscillator clock. In the dual-clock mode, the main-
oscillator can stop oscillating when the STOP instruction is executing or the SCR.1 is set to 1.
When the SCR is set or reset, we must care the following cases:
1. X000B
→
X011B: we should not exchange the F
OSC
from Fm into Fs and disable Fm simultaneously.
We could first exchange the F
OSC
from Fm into Fs, then disable the main-oscillator. So it should be
X000B
→
X001B
→
X011B.
2. X011B
→
X000B: we should not enable Fm and exchange the F
OSC
from Fs into Fm simultaneously.
We could first enable the main-oscillator; the 2nd step is calling a delay subroutine to wait the main-
oscillator oscillating stably; then exchange the F
OSC
from Fs into Fm is the last step. So it should be
X011B
→
X001B
→
delay the Fm oscillating stably time
→
X000B. The suggestion of the Fm oscillating
stably time is 3.5ms for 455K Hz and 0.8ms for 4M Hz.
We must remember that the X010B state is inhibitive, because it will induce the system shutdown.
The organization of the dual-clock operation mode is shown in Figure 6-4.
System Clock
Generator
T1
T2
T3
T4
Main Oscillator
XIN1
XOUT1
Sub-Oscillator
XIN2
XOUT2
Fosc
Divider 0
SCR : System clock Control Register ( default = 00H )
Bit0
Bit1
Bit3
0 : Fosc = Fm
1 : Fosc = Fs
0 : Fm enable
1 : Fm disable
Fm
Fs
enable/disable
SCR.1
STOP
HOLD
SCR.0
LCD Frequency
Selector
F
LCD
Divider 1
INT4
HCF.4
SCR.3(14/12 bit)
1 : 12 bit
0 : 14 bit
Daul clock operation mode :
- SCR.0=0, Fosc=Fm : SCR.0=1, Fosc=Fs
- Flcd=Fs, In STOP mode LCD does not work.
Fosc/128
Dual/Single Colck
Option code is 1/0
Fs or Fosc/128
Figure 6-4 Organization of the dual-clock operation mode