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參數資料
型號: W77IC32-25
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 8 BIT MICROCONTROLLER
中文描述: 8-BIT, 25 MHz, MICROCONTROLLER, PDIP40
封裝: DIP-40
文件頁數: 61/70頁
文件大?。?/td> 375K
代理商: W77IC32-25
Preliminary W77IC32
Publication Release Date: March 2000
- 61 - Revision A0
The master can communicate with all the slaves simultaneously with the Broadcast Address. This
address is formed from the logical ORing of the SADDR and SADEN SFRs. The zeros in the result
are defined as don't cares In most cases the Broadcast Address is FFh. In the previous case, the
Broadcast Address is (1111111X) for slave 1 and (11111111) for slave 2.
The SADDR and SADEN SFRs are located at address A9h and B9h respectively. On reset, these two
SFRs are initialized to 00h. This results in Given Address and Broadcast Address being set as XXXX
XXXX(i.e. all bits don't care). This effectively removes the multiprocessor communications feature,
since any selectivity is disabled.
Timed Access Protection
The W77IC32 has several new features, like the Watchdog timer, on-chip ROM size adjustment, wait
state control signal and Power on/fail reset flag, which are crucial to proper operation of the system. If
left unprotected, errant code may write to the Watchdog control bits resulting in incorrect operation
and loss of control. In order to prevent this, the W77IC32 has a protection scheme which controls the
write access to critical bits. This protection scheme is done using a timed access.
In this method, the bits which are to be protected have a timed write enable window. A write is
successful only if this window is active, otherwise the write will be discarded. This write enable
window is open for 3 machine cycles if certain conditions are met. After 3 machine cycles, this
window automatically closes. The window is opened by writing AAh and immediately 55h to the Timed
Access(TA) SFR. This SFR is located at address C7h. The suggested code for opening the timed
access window is
TA
REG
0C7h
;define new register TA, located at 0C7h
MOV
TA, #0AAh
MOV
TA, #055h
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine
cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the
first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles,
during which the user may write to the protected bits. Once the window closes the procedure must be
repeated to access the other protected bits.
Examples of Timed Assessing are shown below.
Example 1: Valid access
MOV
TA, #0AAh
3 M/C
MOV
TA, #055h
3 M/C
MOV
WDCON, #00h 3 M/C
Note: M/C = Machine Cycles
Example 2: Valid access
MOV
MOV
NOP
SETB EWT
Example 3: Invalid access
MOV
TA, #0AAh
TA, #055h
3 M/C
3 M/C
1 M/C
2 M/C
TA, #0AAh
3 M/C
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