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參數資料
| 型號： | W77LE532 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8 BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數： | 45/85頁 |
| 文件大小： | 2458K |
| 代理商： | W77LE532 |
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Preliminary W77LE532
Publication Release Date: May 14, 2003
- 45 - Revision A1
Table 6. SFR Reset Value, continued
SFR Name
Reset Value
SFR Name
Reset Value
SCON
00000000b
B
00000000b
SBUF
xxxxxxxx
b
EIP
xxx00000b
P2
11111111b
PC
00000000b
SADDR1
00000000b
SADEN1
00000000b
SCON1
00000000b
SBUF1
xxxxxxxx
b
WSCON
00000000b
PMR
010xx0x0b
EXIF
0000
xxx
0b
STATUS
000x0000b
P4
xxxx
1111b
The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset.
External reset
Watchdog reset
Power on reset
WDCON
The POR bit WDCON.6 is set only by the power on reset. The PFI bit WDCON.4 is set when the
power fail condition occurs. However, a power-on reset will clear this bit. The WTRF bit WDCON.2 is
set when the Watchdog timer causes a reset. A power on reset will also clear this bit. The EWT bit
WDCON.1 is cleared by power on resets. This disables the Watchdog timer resets. A watchdog or
external reset does not affect the EWT bit.
0x0x0xx0b
0x0x01x0b
01000000b
INTERRUPTS
The W77LE532 has a two priority level interrupt structure with 12 interrupt sources. Each of the
interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the
interrupts can be globally enabled or disabled.
Interrupt Sources
The External Interrupts
INT
and
bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to
generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine
cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected
and the interrupts request flag IEx in TCON or EXIF is set. The flag bit requests the interrupt. Since
the external interrupts are sampled every machine cycle, they have to be held high or low for at least
one complete machine cycle. The IEx flag is automatically cleared when the service routine is called.
If the level triggered mode is selected, then the requesting source has to hold the pin low till the
interrupt is serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If
the interrupt continues to be held low even after the service routine is completed, then the processor
may acknowledge another interrupt request from the same source. Note that the external interrupts
INT2 to
INT
are edge triggered only. By default, the individual interrupt flag corresponding to
external interrupt 2 to 5 must be cleared manually by software. It can be configured with hardware
cleared by setting the corresponding bit HCx in the T2MOD register. For instance, if HC2 is set
hardware will clear IE2 flag after program enters the interrupt 2 service routine.
0
INT
can be either edge triggered or level triggered, depending on
1
5
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