
W78IRD2/W78IRD2A
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8. INTERRUPTS
This section provides more information about external interrupts
INT2
and
INT3
and provides an
overview of interrupt priority levels and polling sequences.
8.1 External Interrupts 2 and 3
The W78IRD2 offers two additional external interrupts,
INT2
and
INT3
, similar to external interrupts
INT0
and
INT1
in the standard 80C52. These interrupts are configured by the XICON (External
Interrupt Control) register, which is not a standard register in the 80C52. Its address is 0C0H. XICON
is bit-addressable; for example, "SETB 0C2H" sets the EX2 bit of XICON.
8.2 Interrupt Priority
Each interrupt has one of four priority levels in the W78IRD2, as shown below.
Four-level interrupt priority
PRIORITY BITS
IPH.X
IP.X
INTERRUPT PRIORITY LEVEL
0
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest priority)
Interrupts with the same priority level are polled in the sequence indicated below.
Nine-source interrupt information
INTERRUPT SOURCE
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT TYPE
EDGE/LEVEL
VECTOR
ADDRESS
External Interrupt 0
0 (highest)
IE.0
TCON.0
03H
Timer/Counter 0
1
IE.1
-
0BH
External Interrupt 1
2
IE.2
TCON.2
13H
Timer/Counter 1
3
IE.3
-
1BH
Programmable
Counter Array
4
IE.6
-
33H
Serial Port
5
IE.4
-
23H
Timer/Counter 2
6
IE.5
-
2BH
External Interrupt 2
7
XICON.2
XICON.0
3BH
External Interrupt 3
8 (lowest)
XICON.6
XICON.3
43H