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參數資料
型號: W78L801
廠商: WINBOND ELECTRONICS CORP
英文描述: 8-BIT Microcontroller(8位的微控制器)
中文描述: 8位微控制器(8位的微控制器)
文件頁數: 8/20頁
文件大小: 270K
代理商: W78L801
W78L801
- 8 -
Table.1 Priority level for simultaneous requests of the same priority interrupt sources
SOURCE
FLAG
IE0
IQ5
TF0
IQ6
IE1
IQ2
IQ7
TF1
IQ3
IQ8
IQ4
IQ9
PRIORITY LEVEL
(highest)
VECTOR ADDRESS
0003H
0053H
000BH
005BH
0013H
003BH
0063H
001BH
0043H
006BH
004BH
0073H
External Interrupt 0
External Interrupt 5
Timer 0 Overflow
External Interrupt 6
External Interrupt 1
External Interrupt 2
External Interrupt 7
Timer 1 Overflow
External Interrupt 3
External Interrupt 8
External Interrupt 4
External Interrupt 9
(lowest)
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs, a system reset can be caused if it is enabled. The main use of the Watchdog timer is
as a system monitor. This is important in real-time control applications. In case of power glitches or
electro-magnetic interference, the processor may begin to execute errant code. If this is left
unchecked the entire system may crash. The watchdog time-out selection will result in different time-
out values depending on the clock speed. The Watchdog timer will be disabled on reset. In general,
software should restart the Watchdog timer to put it into a known state. The control bits that support
the Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit:
7
6
5
4
-
3
-
2
1
0
ENW
CLRW
WIDL
PS2
PS1
PS0
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2
0 as follows:
PS2 PS1 PS0
0 0 0
0 1 0
PRESCALER SELECT
2
4
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