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參數(shù)資料
型號(hào)： W78LE52P-24
廠商： WINBOND ELECTRONICS CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT MTP MICROCONTROLLER
中文描述： 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 7/22頁(yè)
文件大小： 309K
代理商： W78LE52P-24
Preliminary W78LE52
Publication Release Date: January 1999
- 7 -
Revision A1
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog
timer is as a system monitor. This is important in real-time control applications. In case of power
glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is
left unchecked the entire system may crash. The watchdog time-out selection will result in different
time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In
general, software should restart the Watchdog timer to put it into a known state. The control bits that
support the Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit:
7
6
5
4
-
3
-
2
1
0
ENW
CLRW
WIDL
PS2
PS1
PS0
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2
0 as follows:
PS2 PS1 PS0
0 0 0
0 1 0
0 0 1
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
PRESCALER SELECT
2
4
8
16
32
64
128
256
The time-out period is obtained using the following equation:
1
OSC
2
PRESCALER 1000 12 mS
14
×
×
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
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