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參數資料
型號: W79E201A16FN
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP44
封裝: ROHS COMPLIANT, QFP-44
文件頁數: 29/87頁
文件大?。?/td> 818K
代理商: W79E201A16FN
W79E201
Publication Release Date: December 16, 2004
- 29 -
Revision A2
Accumulator
Bit:
7
6
5
4
3
2
1
0
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
Mnemonic: ACC
Address: E0h
ACC.7-0: The A (or ACC) register is the standard 8052 accumulator.
ADC Control Register
Bit:
7
6
5
4
3
2
1
0
ADC.1
ADC.0
ADCEX
ADCI
ADCS
AADR2 AADR1 AADR0
Mnemonic: ADCCON
Address: E1h
BIT
NAME
FUNCTION
7
ADC.1
Bit 1 of ADC result.
6
ADC.0
Bit 0 of ADC result.
5
ADCEX
Enable external start of conversion by STADC
0 = Conversion can be started by software only (by setting ADCS)
1 = Conversion can be started by software or externally pin P2.0 (by a rising
edge on STADC)
4
ADCI
ADC Interrupt flag: This ADCI flag is set when an A/D conversion result is ready
to be read. An interrupt is invoked if it is enabled. The flag may be cleared by
the interrupt service routine. While this flag is set, the ADC can not start a new
conversion. ADCI can not set by software.
3
ADCS
ADC Start and Status: setting this bit starts an A/D conversion. It may be set by
software or by the external STADC signal. The ADC logic ensures that this
signal is HIGH while the ADC is busy. On completion of the conversion, ADCS
is reset immediately after the interrupt flag has been set. ADCS can not be reset
by software. A new conversion may not be started while either ADCS or ADCI is
high.
ADCI
0
0
1
1
If ADCI is cleared by software while ADCS is set at the same time, a new A/D
conversion with the same channel number may be started.
But it is recommended to reset ADCI
before
ADCS is set.
ADCS
0
1
0
1
ADC Status
ADC not busy; a conversion can be started
ADC busy; start of a new conversion is blocked
Conversion completed; start of a new conversion requires ADCI=0
Conversion completed; start of a new conversion requires ADCI=0
2
AADR2
See the below table.
1
AADR1
See the below table.
0
AADR0
See the below table.
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