
Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 51 -
Revision A2.0
BIT
NAME
FUNCTION
7-6 SCMP [1:0]
Smart fault compare value selector (read/write):
00 = 4
01 = 16
10 = 64
11 = 128
Smart fault sampling frequency selector (read/write):
00 = FOSC/4
01 = FOSC/8
10 = FOSC/16
11 = FOSC/128
Smart fault/brake counter enable (read/write):
0 = Disable, and clear internal smart fault counter.
1 = Enable smart fault detector.
Smart fault/brake counter status (read only):
0 = Counter is non-active.
1 = Counter is active.
Smart fault/brake counters direction status (read only):
0 = Down counting.
1 = Up counting.
Low level smart brake detector:
0 = Disable low level smart brake detector.
1 = Enable low level smart brake detector. It will be cleared by software.
5-4
SFP[1:0]
3
SFCEN
2
SFCST
1
SFCDIR
0
LSBD
ADC PIN SELECT
Bit:
7
6
5
4
3
2
1
0
ADCPS.7
ADCPS.6
ADCPS.5
ADCPS.4
ADCPS.3
ADCPS.2
ADCPS.1
ADCPS.0
Mnemonic: ADCPS
Address: C6h
BIT
NAME
FUNCTION
7-0
ADCPS
ADC input pin select. There are 8 ADC input pins shared with P1.0~P1.7. Its’
functions are controlled by the bit value in ADCPS. Set the bit to switch the
corresponding pin to ADC input port; clear the bit to disable the pin to perform
ADC input port. The reset value is 00H.
BIT
CORRESPONDING PIN
P1.0
P1.1
P1.2
P1.3
BIT
CORRESPONDING PIN
P1.4
P1.5
P1.6
P1.7
ADCPS.0
ADCPS.1
ADCPS.2
ADCPS.3
ADCPS.4
ADCPS.5
ADCPS.6
ADCPS.7
TIMED ACCESS
Bit:
7
6
5
4
3
2
1
0
TA.7
TA.6
TA.5
TA.4
TA.3
TA.2
TA.1
TA.0
Mnemonic: TA
Address: C7h