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參數(shù)資料
| 型號： | W83178S |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100 MHZ 3-DIMM SDRAM BUFFER |
| 中文描述： | W83 SERIES, LOW SKEW CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大小： | 129K |
| 代理商： | W83178S |
Preliminary W83178S
Publication Release Date: March 1999
Revision A1
- 3 -
6. FUNCTIONAL DESCRIPTION
6.1 2-Wire I
2
C Control Interface
The clock generator is a slave I2C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
W83178S initializes with default register settings, and then it
o
ptional to use the 2-wire control
interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA
while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-
high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data
is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address and [1101 0010], command
code checking [0000 0000], and byte count checking. After successful reception of each byte, an
acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to
write to internal I2C registers after the string of data. The sequence order is as follows:
Bytes sequence order for I
2
C controller:
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
Set R/W to 1 when read back the data sequence is as follows:
Clock Address
A(6:0) & R/W
Ack
Byte 0
Ack
Ack
Byte2, 3, 4...
until Stop
Byte 1
6.2 Serial Control Registers
The Pin column lists the affected pin number and the @PowerUp column gives the state at true
power up. Registers are set to the values shown only on true power up. "Command Code" byte and
"Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data
(bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After
that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
6.2.1 Register 0: (1 = Active, 0 = Inactive)
BIT
7
6
5
4
3
2
1
0
@POWERUP
1
1
-
-
1
1
1
1
PIN
11
10
-
-
7
6
3
2
DESCRIPTION
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
Reserved
Reserved
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W83193R-01 | 83.MHZ 3-DIMM CLOCK |
| W83193R-02 | 83.3 MHZ 3-DIMM CLOCK |
| W83193R-04 | 83.3 MHZ 3-DIMM CLOCK |
| W83193R-04A | 83.3 MHZ 3-DIMM CLOCK |
| W83194AR-73 | 150MHZ CLOCK FOR WHITNEY CHIPSET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W83193R-01 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:83.MHZ 3-DIMM CLOCK |
| W83193R-02 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:83.3 MHZ 3-DIMM CLOCK |
| W83193R-04 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:83.3 MHZ 3-DIMM CLOCK |
| W83193R-04A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:83.3 MHZ 3-DIMM CLOCK |
| W83194AR-73 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:150MHZ CLOCK FOR WHITNEY CHIPSET |
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