
W83193R-01
PRELIMINARY
Publication Release Date: May 1998
- 15 - Revision 0.20
10.0 OPERATION OF DUAL FUCTION PINS
Pins 7, 8, 10, 25, and 26 are dual function pins and are used for selecting different functions in this
device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore,
and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these
pins are latched into their appropriate internal registers. Once the correct information are properly
latched, these pins will change into output pins and will be pulled low by default. At the end of the
power up timer (within 3 ms) outputs starts to toggle at the specified frequency.
Within 3ms
Input
Output
Output
tri-state
Output
pull-low
2.5V
Output
tri-state
Output
pull-low
#2 REF0/CPU3.3#_2.5
#7 PCICLK_F/FS1
#8 PCICLK0/FS2
#25 24/MODE
#26 48/FS0
All other clocks
Vdd
Each of these pins are a large pull-up resistor ( 250 k
@3.3V ) inside. The default state will be logic
1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these
dual function pins. Under these conditions, an external 10 k
resistor is recommended to be
connected to Vdd if logic 1 is expected. Otherwise, the direct connection to ground if a logic 0 is
desired. The 10 k
resistor should be place before the serious terminating resistor. Note that these
logic will only be latched at initial power on.
If optional EMI reducing capacitor are needed, they should be placed as close to the series
terminating resistor as possible and after the series terminating resistor. These capacitor has typical
values ranging from 4.7pF to 22pF .