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參數資料
| 型號： | W83194AR-We |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 200MHZ Clock For Whitney Chipset(用于英特爾的WHITNEY型芯片組的頻率為200MHZ時鐘) |
| 中文描述： | 200MHz的時鐘惠特尼芯片組（用于英特爾的惠特尼型芯片組的頻率為200MHz的時鐘） |
| 文件頁數： | 3/16頁 |
| 文件大小： | 270K |
| 代理商： | W83194AR-WE |
W83194AR-We
PRELIMINARY
Publication Release Date: Nov. 1999
- 3 - Revision 0.50
4.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250k
pull-up
4.1 Crystal I/O
SYMBOL
PIN
I/O
FUNCTION
Xin
3
IN
Crystal input with internal loading capacitors(36pF)
and feedback resistors.
Xout
4
OUT
Crystal output at 14.318MHz nominally with internal
loading capacitors(36pF).
4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
SYMBOL
PIN
45,44
I/O
OUT
FUNCTION
CPUCLK [0:1]
Low skew (< 250ps) clock outputs for host
frequencies such as CPU and Chipset.
Power Down mode when driven low.
Clock outputs synchronous with PCI clock and
powered by VddA.
SDRAM clock outputs.
PD#
IOAPIC
SDRAM [ 0:8]
29
47
IN
OUT
41,40,
39,37,36,35,33
,32,31
10
OUT
PCICLK0/ *FS0
I/O
3.3V 33MHz PCI clock during normal operation.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks(Default=1).
Low skew (< 250ps) PCI clock outputs.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks(Default=0).
Low skew (< 250ps) PCI clock outputs.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks(Default=1).
Low skew (< 250ps) PCI clock outputs.
Latched input for APIC_SEL at initial power up for
H/W selecting the output frequency of IOAPIC clock
(Default=1).
Low skew (< 250ps) PCI clock outputs.
3.3V output clocks for the chipset.
PCICLK1/ FS1#
11
I/O
PCICLK2/ *FS2
12
I/O
PCICLK3/*APIC_SEL
14
I/O
PCICLK [ 4:7 ]
3V66 [0:1]
15,17,18,19
7,8
OUT
OUT
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