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W83194AR-73
PRELIMINARY
Publication Release Date: May 1999
Revision 0.30
- 7 -
6.0 SPECIFICATIONS
6.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.
Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).
Symbol
Parameter
Rating
Vdd , V
IN
Voltage on any pin with respect to GND
- 0.5 V to + 7.0 V
T
STG
Storage Temperature
- 65
°
C to + 150
°
C
T
B
Ambient Temperature
- 55
°
C to + 125
°
C
T
A
Operating Temperature
0
°
C to + 70
°
C
6.2 AC CHARACTERISTICS
VddR=Vdd3=VddP=VddS=3.3V 5 %, VddC = VddA= 2.375V~2.9V , T
A
= 0 C to +70 C
Parameter
Symbol
Min
Output Duty Cycle
45
CPU/SDRAM to PCI Offset
t
OFF
1
Skew (CPU-CPU), (PCI-
PCI), (SDRAM-SDRAM)
CPU/SDRAM
Cycle to Cycle Jitter
CPU/SDRAM
Absolute Jitter
Jitter Spectrum 20 dB
Bandwidth from Center
Output Rise (0.4V ~ 2.0V)
& Fall (2.0V ~0.4V) Time
t
THL
Overshoot/Undershoot
Beyond Power Rails
Ring Back Exclusion
V
RBE
0.7
Typ
50
Max
55
4
Units
%
ns
Test Conditions
Measured at 1.5V
15 pF Load Measured at 1.5V
t
SKEW
250
ps
15 pF Load Measured at 1.5V
t
CCJ
ó
250
ps
t
JA
500
ps
BW
J
500
KHz
t
TLH
0.4
1.6
ns
15 pF Load on CPU and PCI
outputs
V
over
0.7
1.5
V
22
at source of 8 inch PCB
run to 15 pF load
2.1
V
Ring Back must not enter this
range.
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相關代理商/技術參數 |
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| W83194R-37 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:100 MHZ AGP CLOCK FOR VIA CHIPSET |
| W83194R-37/-58/-58A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:100MHz/133MHz VIA MVP3. VIA Apollo Pro Clock Gen.. 3-DIMM. with S.S.T. |
| W83194R-39 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:100MHZ 3-DIMM CLOCK |
| W83194R-39/-39A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:100MHz/133MHz（Adding 97MHz）VIA MVP3. VIA Apollo Pro Clock Gen.. 3-DIMM. with S.S.T. |
| W83194R-39A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:100MHZ 3-DIMM CLOCK |
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