
W83627HF/F
PRELIMINARY
Publication Release Date: Jul 1999
Revision 0.53
- 7 -
1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.
I/O8t
I/O12t
I/O12tp3
I/OD12t
I/O24t
OUT12t
OUT12tp3
OD12
OD24
INcs
INt
INtd
INts
INtsp3
- TTL level bi-directional pin with 8 mA source-sink capability
- TTL level bi-directional pin with 12 mA source-sink capability
- 3.3V TTL level bi-directional pin with 12 mA source-sink capability
- TTL level bi-directional pin open drain output with 12 mA sink capability
- TTL level bi-directional pin with 24 mA source-sink capability
- TTL level output pin with 12 mA source-sink capability
- 3.3V TTL level output pin with 12 mA source-sink capability
- Open-drain output pin with 12 mA sink capability
- Open-drain output pin with 24 mA sink capability
- CMOS level Schmitt-trigger input pin
- TTL level input pin
- TTL level input pin with internal pull down resistor
- TTL level Schmitt-trigger input pin
- 3.3V TTL level Schmitt-trigger input pin
1.1
LPC Interface
SYMBOL
PIN
I/O
FUNCTION
CLKIN
18
IN
t
System clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register. Default is 24MHz input.
PME#
PCICLK
19
OD
12
IN
tsp3
O
12tp3
I/OD
12t
Generated PME event.
21
PCI clock input.
LDRQ#
22
Encoded DMA Request signal.
SERIRQ
23
Serial IRQ input/Output.
LAD[3:0]
24-27
I/O
12tp3
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
LFRAME#
LRESET#
SUSCLKIN
29
IN
tsp3
IN
tsp3
IN
ts
Indicates start of a new cycle or termination of a broken cycle.
30
Reset signal. It can connect to PCIRST# signal on the host.
75
32khz clock input , for CIR only.