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參數資料
型號: W83781D
廠商: WINBOND ELECTRONICS CORP
元件分類: 模擬信號調理
英文描述: MONITORING IC
中文描述: SPECIALTY ANALOG CIRCUIT, PQFP48
封裝: LQFP-48
文件頁數: 10/53頁
文件大小: 725K
代理商: W83781D
W83781D
PRELIMINARY
- 5 -
Publication Release Date : Nov. 1997
Revision 0.60
6. PIN DESCRIPTION
I/O
12t
- TTL level bi-directional pin with 12 mA source-sink capability
I/O
12ts
- TTL level and schmitt trigger
OUT
12t
- TTL level output pin with 12 mA source-sink capability
OUT
8t
- TTL level output pin with 8 mA source-sink capability
AOUT
- Output pin(Analog)
OD
8
- Open-drain output pin with 8 mA sink capability
OD
12
- Open-drain output pin with 12 mA sink capability
OD
48
- Open-drain output pin with 48 mA sink capability
IN
t
- TTL level input pin
IN
ts
- TTL level input pin and schmitt trigger
AIN
- Input pin(Analog)
Pin Name
Pin
No.
1
2
3
Type
Description
IOR#
IOW#
CLKIN
IN
ts
IN
ts
IN
t
An active low standard ISA bus I/O Read Control.
An active low standard ISA bus I/O Write Control.
System clock input. Can select 48MHz or 24MHz or 14.318MHz.
The default is 24MHz.
Bi-directional ISA bus Data lines. D0 corresponds to the low order
bit, with D7 the high order bit.
Voltage Supply readouts from P6.This value is read in the VID/Fan
Divisor Register.
+5V V
power. Bypass with the parallel combination of 10
μ
F
(electrolytic or tantalum) and 0.1
μ
F (ceramic) bypass capacitors.
Internally connected to all digital circuitry.
Master reset input.
CASE OPEN. An active high input from an external circuit which
latches a Case Open event. This line can go high without any
clamping action intrusion regardless of the powered state of the
W83781D. The W83781D provides an internal open drain on this
line, controlled by Bit 7 of IRQ Mask Register 2, to provide a
minimum 20 ms reset of this line.
Voltage Supply readouts from P6.This value is read in the bit <0>
of Device ID Register.
0V to +5V amplitude fan tachometer input /
Fan on-off control output. These multifunctional pins can be
programmable input or output.
Serial Bus Clock.
Serial Bus bi-directional Data.
8 mA driver (open drain), active low output with a 20 ms minimum
pulse width. Available when enabled via Bit 7 in SMI# Mask
Register 2.
D7~D0
4-
11
12
I/O
12t
VID1
IN
t
V
CC
(+5V)
13
POWER
GNDD
MR
CASEOPEN
14
15
16
DGROUND
IN
ts
I/O
12t
VID4
17
IN
t
FAN3-FAN1
IN/OUT
18-
20
I/O
12ts
SCL
SDA
RSTOUT#
21
22
23
IN
ts
I/O
12ts
OUT
8t
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