
W83877ATF
Publication Release Date: April 1998
- 50 -
Version 0.51
All Set s registers have a common register which is
Sets Select Register
(SSR)
,
in order to switch to
any
Set
when configuring this register. The summary description of these
Sets
is shown below.
Set
UART
IR
Mode
Sets Description
0
3
3
Legacy/Advanced UART Control and Status Registers.
1
3
3
Legacy Baud Rate Divisor Register.
2
3
Advanced UART Control and Status Registers.
3
3
Version ID
and
Mapped Control Registers.
4
3
Transmitter/Receiver/Timer Counter Registers
and
IR Control Registers.
5
3
Flow Control
and
IR Control
and
Frame Status FIFO Registers.
6
3
IR Physical Layer Control Registers
7
3
Remote Control
and
IR front-end Module Selection Registers.
4.3.2 Set0-Legacy/Advanced UART Control and Status Registers
Address
Offset
Register Name
Register Description
0
RBR/TBR
Receiver/Transmitter Buffer Registers
1
ICR
Interrupt Control Register
2
ISR/UFR
Interrupt Status
or
UART FIFO Control Register
3
UCR/SSR
UART Control
or
Sets Select Register
4
HCR
Handshake Control Register
5
USR
UART Status Register
6
HSR
Handshake Status Register
7
UDR/ESCR
User Defined Register
4.3.2.1 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write)
Receiver Buffer Register is read only and Transmitter Buffer Register is write only. These registers
are described the ame as legacy UART.
In legacy UART, this port only supports PIO mode. In dvanced UART, if setup to MIR/FIR/Remote IR,
this port will support DMA handshake function. Two DMA channels can be used, that is
,
one TX DMA
channel and another RX DMA channel. Therefore, single DMA channel is also supported when the bit
of D_CHSW (DMA Channel Swap, in Set2.Reg2.Bit3) is set and the TX/RX DMA channel is swapped.
Note that two DMA channels are defined in config register CR2A
,
which selects DMA channel or
disables DMA channel. If RX DMA channel is enabled and TX DMA channel is disabled, then the
single DMA channel will be selected.