
W83977F/ W83977AF
PRELIMINARY
Publication Release Date: March 1998
- 58 -
Revision 0.58
4.2.5 Set0.Reg4 - Handshake Control Register (HCR)
Mode
Legacy IR
Advanced IR AD_MD2 AD_MD1 AD_MD0
Reset Value
0
B7
0
B6
0
B5
0
B4
B3
B2
0
B1
0
0
0
B0
0
0
0
XLOOP
SIR_PLS
0
EN_IRQ
TX_WT
0
EN_DMA
0
1
1
Legacy IR Register:
This register controls the pins of IR used for handshaking with peripherals such as modem, and
controls the diagnostic mode of IR.
Bit 4: When this bit is set to logical 1, the legacy IR enters diagnostic mode by an internal loopback:
IRTX is forced to logical 0, and IRRX is isolated from the communication link instead of the
TSR.
Bit 3: The legacy IR interrupt output is enabled by setting this bit to logic 1.
Advanced IR Register:
Bit 7~5
Advanced SIR/ASK-IR, MIR, FIR, Remote Controller Modes:
AD_MD2~0 - Advanced IR/Infrared Mode Select.
These registers are active when Advanced IR Select (ADV_SL, in Set2.Reg2.Bit0) is set
to 1. Operational mode selection is defined as follows. When backward operation
occurs, these registers will be reset to 0 and fall back to legacy IR mode.
AD_MD2~0
(Bit 7, 6, 5)
000
001
010
011
100
101
110
111
Selected Mode
Reserved
Low speed
MIR
(0.576M bps)
Advanced
ASK-IR
Advanced
SIR
High Speed
MIR
(1.152M bps)
FIR
(4M bps)
Consumer IR
Reserved
Bit 4:
MIR, FIR Modes:
SIR_PLS - Send Infrared Pulse
Writing 1 to this bit will send a 2
to signal to SIR that the high speed infrared is still in. This bit will be auto cleared by
hardware.
Other Modes:
Not used.
MIR, FIR modes:
TX_WT - Transmission Waiting
If this bit is set to 1, the transmitter will wait for TX FIFO reaching threshold level or
transmitter time-out before it begins to transmit data which prevents short queues of data
bytes from transmitting prematurely. This is to avoid Underrun.
Other Modes:
Not used.
s long infrared pulse after physical frame end. This is
Bit 3: