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參數資料
| 型號： | W83C43 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Keyboard Controller(鍵盤控制器) |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數： | 13/21頁 |
| 文件大小： | 240K |
| 代理商： | W83C43 |
W83C43
Publication Release Date: January 1996
- 13 -
Revision A2
AC Timing, continued
NO.
DESCRIPTION
MIN.
MAX.
UNIT
T10
RDB to Drive Data Delay
40
nS
T11
RDB to Floating Data Delay
0
20
nS
T12
Data Valid After Clock Falling (SEND)
4
μ
S
μ
S
μ
S
μ
S
μ
S
μ
S
μ
S
mS
T13
K/B Clock Period
20
T14
K/B Clock Pulse Width
10
T15
Data Valid Before Clock Falling (RECEIVE)
4
T16
K/B ACK After Finish Receiving
20
T17
RC Fast Reset Pulse Delay (8 MHz)
2
3
T18
RC Pulse Width (8 MHz)
6
T19
Transmit Timeout
2
T20
Data Valid Hold Time
0
μ
S
nS
T21
X1/X2 Period (6
12 MHz)
Duration of CLK inactive
83
167
T22
30
50
μ
S
μ
S
μ
S
T23
Duration of CLK active
30
50
T24
Time from inactive CLK transition, used to time when
the auxiliary device sample DATA
5
25
T25
Time of inhibit mode
100
300
μ
S
μ
S
μ
S
μ
S
μ
S
T26
Time from rising edge of CLK to DATA transition
5
T28-5
T27
Duration of CLK inactive
30
50
T28
Duration of CLK active
30
50
T29
Time from DATA transition to falling edge of CLK
5
25
T30
Mode detect signal after P10 goes high
Typical 1 mS
T31
High pulse of mode detect signal
Typical 220
μ
S
Typical 220
μ
S
Typical 1 mS
T32
Low pulse of mode detect signal
T33
Mode detect signal after RESET goes high
Time out of AT mode
s mode detect signal
T34
Typical 64 mS
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