
W86L388D
Preliminary
Publication Release Date: August 2001
- 13 -
Revision 0.50
7.2 Card Inserting and Removing
There are two method for Host to detect SD/MMC card inserting or removing through W86L388, the
first method is detected by CD/DAT3 pin, the second method is a dedicate switch on the SD/MMC slot
can be connected to the GIO0 pin and set GIO0 to input direction. These two methods can be
performed even if the W86L388 is in power down state.
Method 1, CD/DAT3 as card detection:
The CD/DAT3 of SD bus can be used as card detection if no data transfer on the DAT3, if SIEN bit on
the control register is low and INS_IE and INT_E on the interrupt enable register are all high, card
inserting or removing will generate interrupt. Host must read the interrupt status register and re-check
the card state by read the CD bit on the extend status register. This detection method will not effective
when wide bus on the SD bus is transfer. MMC card may not support this detection method.
Method 2, GIO0 as card detection:
Some SD/MMC slot support external switch for card existing detection, the switch will on when SD or
MMC is exist. GIO0 with a pull high resister can be used as card detection, the Host can disable the
GOEN0 bit on the general I/O port control register and enable the GIT_EN0 bit on the general I/O port
interrupt enable register and enable GIT_IE and INT_E bits on the interrupt enable register. SD or
MMC card inserting or removing will change the switch state then change the state of GIO0 pin and
then general interrupt to the Host. Host may re-check the card state by read the GIN0 bit on the
general I/O port data register.
7.3 Reset Action
Hardware Reset:
Hardware reset is performed by setting RSTN pin to low state for at least 1 mS. The CPU data size
will set to 16-bit default, all the registers will set to default value. The receive and transmit data buffer
will be cleared; all the internal logic will be reset to initial state.
Software Reset:
Software reset is executed by write the RST bit of the control register to 1, all the internal logic will be
reset to initial state and receive and transmit data buffer will be cleared, but the content of registers
are not affected.
Data Buffer Reset:
Data buffer reset is used to reset the receive data buffer and transmit data buffer simutaneously, the
serial interface command will affected if the data receive or transmit command is progressing. Internal
logic state and the content of registers are not affected.