
Preliminary W91082N
- 2 -
BLOCK DIAGRAM
System Clock
Serial Data
Shift Register
Tone Generator
Control Circuit
CE
XT1
XT1
DATA
CLK
DTMF
FUNCTIONAL DESCRIPTION
The W91082N is a Tone generator with
μ
C serial interface.
When chip enable (
CE
pin goes to low level), the DATA and CLK pins receive the correspondent
code to generate a DTMF signal.
The W91082N defines every digit to have 5 bits code, and D0 (LSB) as the first received bit. The
W91082N latches the data on the falling edge of the clock.
codes and the tone output frequency is shown in Table1. The control timing waveform is shown in
Figure 1.
The relationship between the digital
Digit1 DTMF Signal
Digit2 DTMF Signal
OSC.
CE
CLK
DATA
DTMF
Digit1
Digit2
Stop Code
D0
D4
D0
D4
D0
D4
T
OSC
Figure 1. Serial interface control timing waveform