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參數資料
| 型號： | W981616AH |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 512K x 2 BANKS x 16 BIT SDRAM |
| 中文描述： | 為512k × 2組× 16位SDRAM |
| 文件頁數： | 4/40頁 |
| 文件大小： | 1015K |
| 代理商： | W981616AH |
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W981616BH
- 4 -
FUNCTIONAL DESCRIPTION
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs during power up, all V
CC
and V
CC
Q pins must be ramp up simultaneously to the
specified voltage when the input signals are held in the "NOP" state. The power up voltage must not
exceed V
CC
+0.3V on any of the input pins or V
CC
supplies. After power up, an initial pause of 200
μ
S
is required followed by a precharge of all banks using the precharge command. To prevent data
contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high
during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles
(CBR) are also required before or after programming the Mode Register to ensure proper subsequent
operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of
RAS
,
CAS
,
CS
and
WE
at the positive edge of the clock. The address input data during
this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to t
RSC
has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to
RAS
activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (t
RCD
). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t
RC
).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and
vice versa) is the Bank-to-Bank delay time (t
RRD
). The maximum time that each bank can be held
active is specified as t
RAS
(max.).
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by
setting
RAS
high and
CAS
low at the clock rising edge after minimum of t
RCD
delay.
WE
pin
voltage level defines whether the access cycle is a read operation (
WE
high), or a write operation
(
WE
low). The address inputs determine the starting column address. Reading or writing to a
different row within an activated bank requires the bank be precharged and a new Bank Activate
command be issued. When more than one bank is activated, interleaved bank Read or Write
operations are possible. By using the programmed burst length and alternating the access and
precharge operations between multiple banks, seamless data access operation among many different
pages can be realized. Read or Write Commands can also be issued to the same bank or between
active banks on every clock cycle.
相關PDF資料 |
PDF描述 |
|---|---|
| W981616AH-6 | x16 SDRAM |
| W981616AH-7 | x16 SDRAM |
| W981616AH-8 | x16 SDRAM |
| W9816G6BB | 512K x 2 BANKS x 16 BITS SDRAM |
| W9816G6BB-7 | 512K x 2 BANKS x 16 BITS SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W981616AH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x16 SDRAM |
| W981616AH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x16 SDRAM |
| W981616AH-8 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x16 SDRAM |
| W981616BH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512K ⅴ 2 BANKS ⅴ 16 BITS SDRAM |
| W981616BH-7 | 制造商:Winbond Electronics Corp 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
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