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參數(shù)資料
| 型號： | W9828BADA |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 128MB (16M x 64) PC100 SDRAM MODULE(符合PC100標準的128MB (16M x 64) 同步動態(tài)RAM模塊) |
| 中文描述： | 128MB的（16米x 64）PC100的SDRAM內(nèi)存模組（符合PC100的標準的128MB的（16米x 64）同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 173K |
| 代理商： | W9828BADA |
W9828BADA
128MB (16M x 64) PC100 SDRAM MODULE
Revision 0.9
11 OF 12
Publication Release Date:98/05/18
CONTENTS OF EEPROM (SPD Versions 1.2)
FUNCTION SUPPORTED
HEX VALUE
Byte
Number
FUNCTION DESCRIBED
-8H
-8N
-10
-8H
-8N
-10
0
Defines # bytes written into serial memory at
module manufacturer
Total # bytes of SPD memory device
Fundamental memory type (FPM, EDO, SDRAM..)
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Rows on this assembly
Data Width of this assembly..
..Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycle time @CAS latency of 3
SDRAM Access time form clock @CAS latency of 3
DIMM Configuration type (Non-parity, Parity ECC)
Refresh Rate/Type
SDRAM width , Primary DRAM
Error Checking SDRAM data width
Minimum Clock Delay, Back Random Column
Addresses
Burst Lengths supported
#Bank on Each SDRAM device
CAS# Latencies Supported
CS# Latency
Write Latency
128 bytes
80h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
256 bytes (2K- bit)
SDRAM
12
9
2 row
64 bits
-
LVTTL
10ns
6ns
Non parity
15.625 us, support self refresh
X8
None
08h
04h
0Ch
09h
02h
40h
00h
01h
A0h
60h
00h
80h
08h
00h
8ns
6ns
10ns
8ns
80h
60h
A0h
80h
15
TCCD =1 CLK
01h
16
17
18
19
20
1, 2, 4, 8 & full page
4 banks
2 & 3
0 CLK
0 CLK
Non-buffered Non –registered &
redundant addressing
+/-10% voltage tolerance , Burst
Read, Single bit Write, precharge
all, auto precharge
10ns
12ns
6ns
6ns
-
-
-
-
20ns
20ns
20ns
20ns
20ns
20ns
48ns
48ns
2 row of 64MB .
2ns
2ns
1ns
2ns
2ns
1ns
-
Current release Intel spd 1.2
-
8Fh
04h
06h
01h
01h
21
SDRAM Module Attributes
00h
22
SDRAM Device Attributes: General
0Eh
23
24
25
26
27
28
29
30
31
32
33
34
35
SDRAM cycle time @CAS latency of 2
SDRAM access time form clock @CAS latency of 2
SDRAM cycle time @CAS latency of 1
SDRAM access time from clock @CAS latency of 1
Precharge to active command period (t
RP
)
Active to Active command period (t
RRD
)
Active to Read/Write command delay time(t
RCD
)
Minimum Active to precharge period (t
RAS
)
Density of each Row on Module
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
Data signal input hold time
Superset Information(may be used in future)
SPD Revision
Checksum for Bytes 0-62
Manufacturers code
Manufacturing location
Manufacturer’s Part Number
Revision Code
Manufacturing Date
Assembly Serial Number
Manufacturer Specific Data
System frequency for 100 MHz
Intel Specification details
Unused storage locations
15ns
9ns
-
-
30ns
20ns
30ns
60ns
A0h
60h
00h
00h
14h
14h
14h
30h
C0h
60h
00h
00h
14h
14h
14h
30h
10h
20h
10h
20h
10h
00h
12h
24h
F0h
90h
00h
00h
1Eh
14h
1Eh
3Ch
3ns
20h
30h
3ns
20h
30h
36-61
62
63
64-71
72
73-90
91-92
93-94
95-98
99-125
126
127
128+
E4h
E4h
MFG Dep
MFG Dep
MFG Dep
MFG Dep
MFG Dep
MFG Dep
MFG Dep
64h
F5h
FFh
100MHz
66MHz
66h
06h
Detailed 100MHz Information
F7h
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| W9832AASA | 32MB (4M x 64) SDRAM SO-DIMM MODULE(32MB (4M x 64)小型雙列直插同步動態(tài)RAM模塊) |
| W986408AH | 2M words x 8 bit x 4 Banks SDRAM(2M字 x 8 位 x 4 組同步動態(tài)RAM) |
| W986408BH | 2M words x 8 bit x 4 Banks SDRAM(2M字 x 8 位 x 4 組同步動態(tài)RAM) |
| W986408CH | 2M x 8BIT x 4 BANKS SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W986408CH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M x 8BIT x 4 BANKS SDRAM |
| W986408CH-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
| W986408CH-8H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
| W986416CH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M x 16 BIT x 4 BANKS SDRAM |
| W986416CH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x16 SDRAM |
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