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參數資料
| 型號： | W9864AASA |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64MB (8M x 64) SDRAM SO-DIMM MODULE(64MB (8M x 64)小型雙列直插同步動態RAM模塊) |
| 中文描述： | 64MB的（8米× 64）SDRAM內存的SO - DIMM模組（64兆（8米× 64）小型雙列直插同步動態內存模塊） |
| 文件頁數： | 7/12頁 |
| 文件大小： | 166K |
| 代理商： | W9864AASA |
W9864AASA
64MB (8M x 64) SDRAM SO-DIMM MODULE
Revision 0.9
7 OF
12
Publication Release Date:98/05/18
AC CHARACTERISTICS AND OPERATING CONDITION
( Vcc=3.3V
±
0.3V, Ta=0
°
to 70
°
C )
- 10
10L
SYMBOL
PARAMETER
MIN
90
60
30
MAX
MIN
90
60
30
MAX
UNIT
t
RC
t
rAS
t
RCD
Ref/Active to Ref/Active Command Period
Active to precharge Command Period
Active to Read/Write Command Delay Time
Read/Write(a) to Read/Write(b)Command
Period
Precharge to Active(b) Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
100000
100000
ns
t
CCD
1
1
cycle
t
RP
t
RRD
30
20
15
10
15
10
3
3
30
20
15
10
15
10
3
3
CL*=2
CL*=3
CL*=2
CL*=3
1000
1000
1000
1000
t
WR
CLK Cycle Time
t
CK
t
CH
t
CL
CLK High Level
CLK Low Level
Access Time from CLK
CL*=2
CL*=3
9
8
9
8
t
AC
ns
t
OH
t
HZ**
t
LZ
t
SB
t
T
t
DS
t
DH
t
AS
t
AH
t
CKS
t
CKH
t
CMS
t
CMH
t
REF
t
RSC
Output Data Hold Time
Output Data High Impedance Time
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK (Rise and Fall)
Data-in-Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode register Set Cycle Time
Note
:
*CL=CAS Latency
** t
HZ
defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
Refer to the individual component
3
3
0
0
3
3
0
0
10
10
10
10
10
10
0.5
3
1
3
1
3
1
3
1
0.5
3
1
3
1
3
1
3
1
64
64
ms
ns
20
20
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