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參數資料
| 型號： | WB1356 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual Serial Input PLL with 2.0- and 1.1-GHz Prescalers(帶2.0-GHz1.1-GHz 預標定器的雙路串聯輸入PLL) |
| 中文描述： | 雙串行輸入鎖相環和1.1與2.0 GHz的分頻器（帶2.0 - GHz1.1 - GHz的預標定器的雙路串聯輸入鎖相環） |
| 文件頁數： | 3/10頁 |
| 文件大小： | 157K |
| 代理商： | WB1356 |
WB1356
3
Pin Definitions
Pin Name
V
CC
1
Pin
No.
1
Pin
Type
P
Pin Description
Power Supply Connection for PLL1 and PLL2:
When power is removed from both
the V
CC
1 and V
CC
2 pins, all latched data is lost.
PLL1 Charge Pump Rail Voltage:
This voltage accommodates VCO circuits with
tuning voltages higher than the V
CC
of PLL1.
PLL1 Charge Pump Output:
The phase detector gain is I
P
/2
π
. Sense polarity can
be reversed by setting the FC bit in software (via the Shift Register).
V
P
1
2
P
D
O
PLL1
3
O
GND
4
G
Analog and Digital Ground Connection:
This pin must be grounded.
Input to PLL1 Prescaler:
Maximum frequency 2.0 GHz.
F
IN
1
F
IN
1#
5
I
6
I
Complementary Input to PLL1 Prescaler:
A bypass capacitor should be placed as
close as possible to this pin and must be connected directly to the ground plane.
GND
7
G
Analog and Digital Ground Connection:
This pin must be grounded.
Oscillator Input:
This input has a V
CC
/2 threshold and CMOS logic level sensitivity.
Oscillator Output
Lock Detect Pin:
This output is HIGH when the loop is locked. It is multiplexed to the
output of the programmable counters or reference dividers in the test program mode.
(Refer to
Table 3
for configuration.)
Data Clock Input:
On the rising edge, one bit of data is loaded into the Shift Register.
OSC_IN
8
I
OSC_OUT
9
O
F
O
/LD
10
O
CLOCK
11
I
DATA
12
I
Serial Data Input
Load Enable:
On the rising edge of this signal, the data stored in the Shift Register
is latched into the counters and configuration controls, PLL1 or PLL2 depending on
the control bit states.
LE
13
I
GND
14
G
Analog and Digital Ground Connection:
This pin must be grounded.
Complementary Input to PLL2 Prescaler:
A bypass capacitor should be placed as
close as possible to this pin and must be connected directly to the ground plane.
F
IN
2#
15
I
F
IN
2
GND
16
I
Input to PLL2 Prescaler:
Maximum frequency 1.1 GHz.
Analog and Digital Ground Connections:
This pin must be grounded.
PLL2 Charge Pump Output:
The phase detector gain is I
P
/2
π
. Sense polarity can
be reversed by setting the FC bit in software (via the Shift Register).
17
G
D
O
PLL2
18
O
V
P
2
19
P
PLL2 Charge Pump Rail Voltage:
This voltage accommodates VCO circuits with
tuning voltages higher than the V
CC
of PLL2.
Power Supply Connections for PLL1 and PLL2:
When power is removed from both
the V
CC
1 and V
CC
2 pins, all latched data is lost.
V
CC
2
20
P
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