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參數資料
| 型號： | 4450HA/3-K |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, PBGA324 |
| 封裝： | HSBGA-324 |
| 文件頁數： | 16/92頁 |
| 文件大小： | 780K |
| 代理商： | 4450HA/3-K |
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4450 – Data Sheet, DS-0131-06
Page 23
Hifn Confidential
4
4450 Operation
4.1 4450 Chip Architecture
The 4450 FlowThrough Security Processor contains several processing units comprising two
major subsystems.
The “control path” subsystem contains the embedded Session Controller (eSC), Random
Number Generator (RNG), the Public Key processor and an RMII interface for an out-of-
band host control port or inter-chip communications in multi-chip applications. The eSC
subsystem hosts the IKE protocol & exception handling and provides public key and RNG
services.
Figure 4-1. 4450 Block Diagram
The “fast data path” packet handling subsystem consists of all the blocks necessary for
packet parsing and classification as well as the blocks to perform IPsec and IPcomp
processing. Four full-duplex GbE MAC (Media Access Controller) cores provide the primary
packet I/O. The packets are automatically moved through the crypto-processing pipeline
via the Packet Queue Manager and DMA engines. The programmable DPU and PCP
processors perform hardware-assisted packet policy look-up, SA look-up, and packet
header and trailer processing.
ECC DDR2
SDRAM
Public-Key
Engine
Control
Port
(RMII)
32/39- bit
Crypto
Engine 0
SA
RAM
Data
RAM
Code
RAM
Post
Crypto
Proc. 0
Post
Crypto
Proc. 1
DMA
Packet
Queue
Manager
Bridge
Crypto
Engine1
H0
RGMII/
RTBI
MAC
Policy
TCAM
RNG
eSC
(Control Path)
DPU
(Fast Path)
Memory Bridge
Data
RAM
Code
RAM
Post
Crypto
Processor
(Fast Path)
SGMII/
SerDes
SerD
es
N1
H1
SGMII/
SerDes
Se
rD
es
N0
SGMII/
SerDes
Buffer
Gb
E
M
A
C
Se
rD
es
H1
Buffer
Gb
E
MAC
Buffer
GbE
MA
C
N1
SGMII/
SerDes
Buffer
GbE
MA
C
Se
rD
es
H0
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