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參數資料
型號: 951416AFLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產生/分配
英文描述: 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 0.300 INCH, 0.025 INCH PITCH, GREEN, MO-118, SSOP-56
文件頁數: 5/27頁
文件大小: 248K
代理商: 951416AFLF
13
ICS951416
0937H—05/26/05
SMBus Table: CPU Spread Spectrum Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
Reserved
R
-
0
Bit 6
SSP14
RW
X
Bit 5
SSP13
RW
X
Bit 4
SSP12
RW
X
Bit 3
SSP11
RW
X
Bit 2
SSP10
RW
X
Bit 1
SSP9
RW
X
Bit 0
SSP8
RW
X
SMBus Table: SRC Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
N Div8
N Divider Prog bit 8
RW
X
Bit 6
N Div9
N Divider Prog bit 9
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
RW
X
SMBus Table: SRC Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
N Div7
RW
X
Bit 6
N Div6
RW
X
Bit 5
N Div5
RW
X
Bit 4
N Div4
RW
X
Bit 3
N Div3
RW
X
Bit 2
N Div2
RW
X
Bit 1
N Div1
RW
X
Bit 0
N Div0
RW
X
SMBus Table: SRC Spread Spectrum Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SSP7
RW
X
Bit 6
SSP6
RW
X
Bit 5
SSP5
RW
X
Bit 4
SSP4
RW
X
Bit 3
SSP3
RW
X
Bit 2
SSP2
RW
X
Bit 1
SSP1
RW
X
Bit 0
SSP0
RW
X
Byte 14
-
Byte 15
-
Byte 17
These Spread Spectrum
bits in Byte 13 and 14
will program the spread
pecentage of CPU
The decimal
representation of M and
N Divier in Byte 15 and
16 will configure the
SRC VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
The decimal
representation of M and
N Divier in Byte 15 and
16 will configure the
SRC VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency =
These Spread Spectrum
bits in Byte 17 and 18
will program the spread
pecentage of SRC
-
Spread Spectrum
Programming bit(14:8)
-
N Divider Programming
b(7:0)
-
M Divider Programming
bits
-
Byte 16
Spread Spectrum
Programming b(7:0)
-
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