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參數資料
型號: 951416AFLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產生/分配
英文描述: 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 0.300 INCH, 0.025 INCH PITCH, GREEN, MO-118, SSOP-56
文件頁數: 6/27頁
文件大小: 248K
代理商: 951416AFLF
14
ICS951416
0937H—05/26/05
SMBus Table: SRC Spread Spectrum Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
Reserved
R
-
0
Bit 6
SSP14
RW
X
Bit 5
SSP13
RW
X
Bit 4
SSP12
RW
X
Bit 3
SSP11
RW
X
Bit 2
SSP10
RW
X
Bit 1
SSP9
RW
X
Bit 0
SSP8
RW
X
SMBus Table: Programmable Output Divider Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
CPUDiv3
RW
X
Bit 6
CPUDiv2
RW
X
Bit 5
CPUDiv1
RW
X
Bit 4
CPUDiv0
RW
X
Bit 3
HTTDiv3
RW
X
Bit 2
HTTDiv2
RW
X
Bit 1
HTTDiv1
RW
X
Bit 0
HTTDiv0
RW
X
SMBus Table: Programmable Output Divider Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRC_Div3
RW
X
Bit 6
SRC_Div2
RW
X
Bit 5
SRC_Div1
RW
X
Bit 4
SRC_Div0
RW
X
Bit 3
ATIG_Div3
RW
X
Bit 2
ATIG_Div2
RW
X
Bit 1
ATIG_Div1
RW
X
Bit 0
ATIG_Div0
RW
X
HTT Divider Ratio
Programming Bits (PCI
divider is always 2x the
HTT divider or 1/2 freq.)
-
Byte 19
Byte 18
These Spread Spectrum
bits in Byte 17 and 18
will program the spread
pecentage of SRC
CPU Divider Ratio
Programming Bits
-
Spread Spectrum
Programming b(14:8)
-
Byte 20
-
See Table 3: CPU
Divider Ratios
See Table 4: HTT
Divider Ratios
See Table 5: SRC and
ATIG Divider Ratios
-
ATIG_ Divider Ratio
Programming Bits
-
SRC_ Divider Ratio
Programming Bits
相關PDF資料
PDF描述
951416AGLFT 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
951462YGLFT PROC SPECIFIC CLOCK GENERATOR, PDSO64
951464YFLFT 240 MHz, OTHER CLOCK GENERATOR, PDSO56
951601AFLF 66.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
951901AF 133.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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