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參數資料
| 型號： | 992215735021 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CPGA76 |
| 封裝： | PGA-76 |
| 文件頁數： | 14/17頁 |
| 文件大小： | 171K |
| 代理商： | 992215735021 |
1999 September
6
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Timing diagrams (for default operation)
C1 to C3: Horizontal register clocks
SSC: Start-Stop C-clocks
SG: Summing gate
RG: Reset gate
VD: Frame pulse
CR: Charge Reset
BLC: Black Level Clamp
B1 to B4: Vertical storage clocks
1 Tp = 1 clock period
2 Duty cycle = 50% and phase shift of the C clocks is 120 degrees.
AC CHARACTERISTICS
MIN.
TYPICAL
MAX.
UNIT
Horizontal frequency (1/Tp)
1
Vertical frequency
Charge Reset (CR) time
Rise and fall times:
image clocks (A)
storage clocks (B)
register clocks (C)
2
summing gate (SG)
reset gate (RG)
0
2
10
3
18
450
5
20
5
40
1000
1/6 Tp
MHz
kHz
s
ns
Figure 3 - Line and pixel timing diagrams
SSC
B1
B2
B3
B4
CR
AHigh
VD
BLC
C1
C2
C3
SG
RG
SSC
Tp = 1 clock period = 1 / 18MHz = 55.56ns
Pixel output sequence: 7 dummy, 20 black, 4 timing, 1024 active, 4 timing, 20 black
Line Time: 1184 x Tp = 65.7s
Line Timing
Pixel Timing
* During AHigh = H the phiA high level is increased from 10V to 14V
*
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
1Tp
1079 pixels
Tp / 6
105Tp
34Tp
15Tp
25Tp
24Tp
14Tp
19Tp
Tp
105
Tp
101
Tp
2
141Tp
30Tp
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