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參數資料
| 型號： | AD7660AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS CMOS ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數： | 6/20頁 |
| 文件大小： | 218K |
| 代理商： | AD7660AST |
REV. 0
AD7660
–6–
Pin
No.
Mnemonic
Type
Description
22
DATA[9]
DI/O
When SER/
PAR
is LOW, this output is used as the Bit 9 of the Parallel Port Data Output
Bus.
When SER/
PAR
is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/
INT
pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
When SER/
PAR
is LOW, this output is used as the Bit 10 of the Parallel Port Data Output
Bus.
When SER
/PAR
is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
INT
= Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH
while SDOUT output is valid. When a read sequence is initiated and INVSYNC is High,
SYNC is driven LOW and remains LOW while SDOUT output is valid.
When SER/
PAR
is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH and EXT/
INT
is HIGH, this output, part of the serial port, is used
as an incomplete read error flag. In slave mode, when a data read is started and not complete
when the following conversion is complete, the current data is lost and RDERROR is pulsed high.
Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regard-
less of the state of SER/
PAR
.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data ready clock signal.
Must be tied to digital ground.
Read Data. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is
enabled.
RD
and
CS
are OR’d together internally.
Chip Select. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is
enabled.
RD
and
CS
are OR’d together internally.
Reset Input. When set to a logic HIGH, reset the AD7660. Current conversion if any is aborted.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver-
sions are inhibited after the current one is completed.
Start Conversion. If
CNVST
is HIGH when the acquisition phase (t
8
) is complete, the next
falling edge on
CNVST
puts the internal sample/hold into the hold state and initiates a con-
version. This mode is the most appropriate if low sampling jitter is desired. If
CNVST
is LOW
when the acquisition phase (t
8
) is complete, the internal sample/hold is put into the hold state
and a conversion is immediately started.
Must be tied to analog ground.
Reference Input Voltage.
Reference Input Analog Ground.
Analog Input Ground.
Primary analog input with a range of 0 V to V
REF.
or SCLK
23
DATA[10]
DO
or SYNC
24
DATA[11]
or RDERROR
DO
25–28
DATA[12:15]
DO
29
BUSY
DO
30
31
DGND
RD
P
DI
32
CS
DI
33
34
RESET
PD
DI
DI
35
CNVST
DI
36
37
38
39
43
AGND
REF
REFGND
INGND
IN
P
AI
AI
AI
AI
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
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