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參數資料
| 型號： | AD7801 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | +2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC |
| 中文描述： | 2.7 V至5.5 V，電壓并行輸入輸出8位DAC |
| 文件頁數： | 8/16頁 |
| 文件大小： | 219K |
| 代理商： | AD7801 |
AD7801
–8–
REV. 0
Reference
T he AD7801 has the ability to use either an external reference
applied through the REFIN pin or an internal reference generated
from V
DD
. Figure 20 shows the reference input arrangement
where either the internal V
DD
/2 or the externally applied reference
can be selected.
T he internal reference is selected by tying the REFIN pin to
V
DD
. If an external reference is to be used, this can be directly
applied to the REFIN pin and if this is 1 V below V
DD
, the
internal circuitry will select this externally applied reference as
the reference source for the DAC.
Digital Interface
T he AD7801 contains a fast parallel interface allowing this
DAC to interface to industry standard microprocessors,
microcontrollers and DSP machines. T here are two modes in
which this parallel interface can be configured to update the
DAC output. T he synchronous update mode allows synchro-
nous updating of the DAC output; the automatic update mode
allows the DAC to be updated individually following a write
cycle. Figure 21 shows the internal logic associated with the
digital interface. T he PON ST RB signal is internally generated
from the power-on reset circuitry and is low during the power-
on reset phase of the power up procedure.
CLEAR
SET SLE
LDAC
ENABLE
DAC CONTROL
LOGIC
MLE
SLE
CLR
PON STRB
CLR
LDAC
CS
WR
Figure 21. Logic Interface
T he AD7801 has a double buffered interface, which allows for
synchronous updating of the DAC output. Figure 22 shows a
block diagram of the register arrangement within the AD7801.
MLE
SLE
CONTROL LOGIC
CS
WR
LDAC
CLR
4
15
15
30
8
I
R
4
D
D
R
4
15
15
30
4
D
D
R
D
LOWER
NIBBLE
UPPER
NIBBLE
DB7-DB0
D
Figure 22. Register Arrangement
Automatic Update Mode
In this mode of operation the
LDAC
signal is permanently tied
low. T he state of the
LDAC
is sampled on the rising edge of
WR
.
LDAC
being low allows the DAC register to be automati-
cally updated on the rising edge of
WR
. T he output update
occurs on the rising edge of
WR
. Figure 23 shows the timing
associated with the automatic update mode of operation and
also the status of the various registers during this frame.
HOLD
HOLD
TRACK
TRACK
D7-D0
WR
CS
LDAC
= 0
I/P REG (MLE)
DAC REG (SLE)
V
OUT
TRACK
HOLD
Figure 23. Timing and Register Arrangement for Auto-
matic Update Mode
Synchronous Update Mode
In this mode of operation the
LDAC
signal is used to update the
DAC output to synchronize with other updates in the system.
T he state of the
LDAC
is sampled on the rising edge of
WR
. If
LDAC
is high, the automatic update mode is disabled and the
DAC latch is updated at any time after the write by taking
LDAC
low. T he output update occurs on the falling edge of
LDAC
.
LDAC
must be taken back high again before the next
data transfer takes place. Figure 24 shows the timing associated
with the synchronous update mode of operation and also the
status of the various registers during this frame.
HOLD
HOLD
D7-D0
WR
CS
LDAC
I/P REG (MLE)
DAC REG (SLE)
V
OUT
HOLD
HOLD
TRACK
TRACK
Figure 24. Timing and Register Arrangement for Synchro-
nous Update Mode
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| AD7801BR | 功能描述:IC DAC 8BIT 2.7V 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 產品培訓模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標準包裝:91 系列:- 設置時間:4µs 位數:10 數據接口:MICROWIRE?，串行，SPI? 轉換器數目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應商設備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD7801BR-REEL | 制造商:Analog Devices 功能描述:DAC 1-CH Current Steering 8-bit 20-Pin SOIC W T/R |
| AD7801BR-REEL7 | 制造商:Analog Devices 功能描述:DAC 1-CH Current Steering 8-bit 20-Pin SOIC W T/R 制造商:Analog Devices 功能描述:DAC 1CH CURRENT STEERING 8BIT 20SOIC W - Tape and Reel |
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