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參數(shù)資料
| 型號： | AD7923BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Four Wall Header; No. of Contacts:60; Pitch Spacing:0.1"; No. of Rows:2; Gender:Header; Body Material:Glass-filled Polyester; Contact Plating:Nickel; Leaded Process Compatible:No; Mounting Type:Through Hole RoHS Compliant: No |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 430K |
| 代理商： | AD7923BRU |
AD7923
–9–
REV. 0
Table I. Control Register Bit Functions
MSB
WRITE
LSB
CODING
SEQ1 DONTC
DONTC
ADD1 ADD0
PM1
PM0
SEQ0
DONTC
RANGE
Bit
Mnemonic
Comment
11
WRITE
The value written to this bit of the Control Register determines whether the following 11 bits will be
loaded to the Control Register. If this bit is a 1, the following 11 bits will be written to the Control Register;
if it is a 0, the remaining 11 bits are not loaded to the Control Register and it remains unchanged.
The SEQ1 bit in the Control Register is used in conjunction with the SEQ0 bit to control the use of the
sequencer function. (See Table IV.)
Don’t Care
ADD1, ADD0
These two address bits are loaded at the end of the present conversion and select which analog input channel is
to
be converted in the next serial transfer, or they may select the final channel in a consecutive sequence as described
in Table IV. The selected input channel is decoded as shown in Table II. The address bits corresponding to
the conversion result are also output on DOUT prior to the 12 bits of data. (See the Serial Interface section.)
The next channel to be converted on will be selected by the mux on the 14th SCLK falling edge.
PM1, PM0
Power Management Bits. These two bits decode the mode of operation of the AD7923 as shown in Table III.
SEQ0
The SEQ0 bit in the Control Register is used in conjunction with the SEQ1 bit to control the use of the
sequencer function. (See Table IV.)
DONTC
Don’t Care
RANGE
This bit selects the analog input range to be used on the AD7923. If it is set to 0, the analog input range
will extend from 0 V to 2
￥
REF
IN
. If it is set to 1, the analog input range will extend from 0 V to REF
IN
(for
the next conversion). For the 0 V to 2
￥
REF
IN
range, AV
DD
= 4.75 V to 5.25 V.
CODING
This bit selects the type of output coding the AD7923 will use for the conversion result. If this bit is set to 0,
the output coding for the part will be twos complement. If this bit is set to 1, the output coding from the
part will be straight binary (for the next conversion).
10
SEQ1
9–8
7–6
DONTC
5, 4
3
2
1
0
CODE
1.0
0
4096
I
0
–0.4
–0.8
–1.0
0.2
–0.2
–0.6
2048
0.6
AV
= V
= 5V
TEMP = 25 C
0.4
0.8
2560
3072
3584
512
1024
1536
TPC 6. Typical INL
CONTROL REGISTER
The Control Register on the AD7923 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7923 on the falling
edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data
transferred on the DIN line corresponds to the AD7923 configuration for the next conversion. This requires 16 serial clocks for every
data transfer. Only the information provided on the first 12 falling clock edges (after
CS
falling edge) is loaded to the Control Register.
MSB denotes the first bit in the data stream. The bit functions are outlined in Table I.
CODE
1.0
0
4096
D
0
–0.4
–0.8
–1.0
0.2
–0.2
–0.6
2048
0.6
0.4
0.8
2560
3072
3584
512
1024
1536
AV
DD
= V
DRIVE
= 5V
TEMP = 25 C
TPC 7. Typical DNL
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