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CHAPTER 14 UART/SIO
Figure 14.8-4 8-bit Data Receiving Operation in CLK Synchronous Mode
I
Continuous Receiving Operation
In CLK synchronous mode, not only an 8-bit data receiving operation but also a continuous
receiving operation can be performed. In the continuous receiving operation, the TIE bit in the
SMC2 register and the TDRE bit in the SSD register are used in addition to the registers used in
the 8-bit data receiving operation. The receiving operation is permitted by setting the TXE/RXE
bits to "11" and started by writing to the SODR register. The receiving operation is performed in
synch with the rising edge of the shift clock. When a shift operation starts, the TDRE bit is set to
"1." When TIE is "1" at this time, an interrupt to the CPU is generated. By writing to the SODR
register before the shift operation of 8-bit data is completed, the next shift operation is permitted
and the receiving operation is performed continuously after the reception of 8-bit data. When
the reception of 8-bit data is completed, the data in the shifter is loaded to the SIDR register and
the RDRF flag is set to "1." When RIE is "1" at this time, an interrupt request to the CPU is
generated. If an overrun error is detected at the end of reception, data is not loaded to the
SIDR register and the description in the SIDR register is the previously received data. By
reading the SIDR register, a reception interrupt (RDRF) is cleared. By writing "0" to the RXE bit,
the receiving operation is stopped. If "0" is written to the RXE bit during the receiving operation,
the receiving operation is stopped after 8-bit data is received.
SI
D0
D1
D2
D3
D4
D5
D6
D7
SCK
Load to
SIDR
RDRF
Write to
SODR
Interrupt to CPU