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參數資料
型號: TLV2556MPWREP
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, PLASTIC, TSSOP-20
文件頁數: 16/37頁
文件大小: 705K
代理商: TLV2556MPWREP
MSB
1
2
3
5
4
6
10
11
12
1
MSB1 MSB2 MSB3 MSB4 MSB5
MSB8 MSB9 LSB+1
LSB
2
3
D6
D5
8
7
9
MSB6 MSB7
D7
Low Level
MSB
D6
D5
D4
D3
D2
D1
D0
D7
MSB2
MSB1
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
Access
Cycle
Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
tconv
Previous Conversion Data
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
INT
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
1
2
3
5
4
6
1
MSB1 MSB2 MSB3 MSB4 MSB5 LSB+1
LSB
HiZ State
2
3
D6
D5
D4
D3
D2
D1
D0
D6
D5
D7
8
7
D7
MSB
MSB2
MSB1
4
5
6
7
D4
D3
MSB4
MSB3
D2
D1
MSB6
MSB5
Access
Cycle
Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
tconv
Previous Conversion Data
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
INT
Initialize
www.ti.com ................................................................................................................................................... SLAS598A – NOVEMBER 2008 – REVISED JULY 2009
PARAMETER MEASUREMENT INFORMATION (continued)
A.
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 47. Timing for 12-Clock Transfer Not Using CS With DATA OUT Set for MSB First
A.
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 48. Timing for 8-Clock Transfer Using CS With DATA OUT Set for MSB First
Copyright 2008–2009, Texas Instruments Incorporated
23
Product Folder Link(s): TLV2556-EP
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