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參數資料
| 型號： | W312-02HT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | FTG for VIA K7 Series Chipset with Programmable Output Frequency |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數： | 3/21頁 |
| 文件大小： | 143K |
| 代理商： | W312-02HT |
W312-02
Document #: 38-07259 Rev. *B
Page 3 of 21
PD#
34
I
Power-Down Input:
This input will trigger the clock generator into Power
Down mode when it is active.
Data pin for SMBus circuitry.
Clock pin for SMBus circuitry.
2.5V Power Connection:
Power supply for CPU output buffers. Connect to
2.5V.
3.3V Power Connection:
Power supply for AGP output buffers. Connect to
3.3V.
3.3V Power Connection:
Power supply for PCI output buffers. Connect to
3.3V.
3.3V Power Connection:
Power supply for 48 MHz output buffers. Connect
to 3.3V.
3.3V Power Connection:
Power supply for reference output buffers. Connect
to 3.3V.
3.3V Power Connection:
Power supply for PLL core. Connect to 3.3V.
Ground Connections:
Connect all ground pins to the common system ground
plane.
SDATA
SCLK
VDD_CPU
31
30
40
I/O
I
P
VDDQ_AGP
25
P
VDDQ_PCI
15, 23
P
VDDQ_48MHz
5
P
VDD_REF
1
P
VDD_Core
GND_REF,
GND_48MHz,
GND_PCI,
GND_AGP,
GND_Core,
GND_CPU
33
P
G
2, 8, 29, 32, 37,
43
Pin Definitions
(continued)
Pin Name
Pin No.
Pin
Type
Pin Description
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