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參數資料
型號: W6693A
廠商: WINBOND ELECTRONICS CORP
英文描述: USB Bus ISDN S/T Interface Controller(USB總線的ISDN S/T接口控制器)
中文描述: USB總線綜合業務數字網的S / T接口控制器(綜合業務數字網的USB總線的S / T的接口控制器)
文件頁數: 24/32頁
文件大小: 423K
代理商: W6693A
Preliminary Data Sheet
W6694 Passive USB-ISDN S/T-Controller
-24-
Publication Release Date: March., 2000
Revision 0.93
1: The previous transmission is in progress.
Test Loopback
When set this bit both the GCIDU and GCIDD lines are internally connected together. The GCI mode loopback test
function: GCIDU is internally connected with GCIDD, external input on GCIDD is ignored.
GRLP GCI Mode Remote Loopback
Setting this bit to 1 activates the remote loopback function. The 2B+D channels data received from the GCI bus
interface are looped to the transmitted channels.
SPU
Software Power Up
PD
Power Down
SPU
PD
0
1
After U transceiver power down, W6694 will receive the indication DC (Deactivation Confirmation) from
GCI bus and then software has to set SPU
0, PD
1 to acknowledge U transceiver, by pulling GCIDU
line to HIGH. W6694 remains normal operation.
1
0
Setting SPU
1, PD
0 will pull the GCI bus GCIDU line to LOW. This will enforce connected layer 1
devices (U transceiver) to deliver GCI bus clocking.
0
0
After reception of the indication PU (Power Up indication) the reaction of the microprocessor should be:
-
To write an AR (Activate Request command) as C/I command code in the CIX register.
- To reset the SPU bit and wait for the following ICC (indication code change) interrupt.
1
1
Unused.
GE
GCI Mode Enable
Setting this bit to 1 will enable the GCI bus interface. In the same time, the S/T layer 1 function is disabled.
TLP
Description
8.3.2 Monitor Channel Control Register
Value after reset: 00h
7
6
0
0
MRIE Monitor Channel 0 Receive Interrupt Enable
Monitor channel interrupt status MDR, MER generation is enabled (1) or masked (0).
MRC MR Bit Control
Determines the value of the MR bit:
0: MR bit always 1. In addition, the MDR interrupt is blocked, except for the first byte of a packet (if MRIE=1).
1: MR internally controlled according to Monitor channel protocol. In addition, the MDR interrupt is enabled for all
bytes according to the Monitor channel protocol (if MRIE=1).
MXIE Monitor Channel Transmit Interrupt Enable
Monitor interrupt status MDA, MAB generation is enabled (1) or masked (0).
MXC MX Bit Control
Determines the value of the MX bit:
0: MX always 1.
MOCR
Read/Write Address 07h
5
0
4
0
3
2
1
0
MRIE
MRC
MXIE
MXC
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