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參數(shù)資料
| 型號： | W741E20X |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 4-BIT FLASH MICROCONTROLLER |
| 中文描述： | 4位閃存微控制器 |
| 文件頁數(shù)： | 20/84頁 |
| 文件大小： | 531K |
| 代理商： | W741E20X |
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Preliminary W741E20X
- 20 -
Output Port RE
Output port RE can be used as an output of the internal RT port, or as a serial input/output port. The
control flow is shown in Figure 8. When bit 1 of port mode 3 register (PM3) equals to 0, port RE works
as an output of internal port RT. When the MOV RE, R instruction is executed, the data in the RAM will
be output to port RT through port RE. When RE works as a parallel output port, it provides a high sink
current to drive LEDs. When bit 1 of MR0 equals to 1, the RE port works as a serial input/output port,
and RE.0 to RE.3 are used as DOUT, CLKO, DIN, and CLKI, respectively. In this case, the DIN pin
will has a built-in pull-high resistor. The serial I/O functions are controlled by the instructions SOP R
and SIP R. The functions of the two instructions are described below:
(1) When the SIP R instruction is executed, the data will be loaded from the serial input buffer to the
ACC and RAM first, and bit 1 of port status register 2 will automatically be set to "1" (BUSYI = 1).
Then the CLKI pin will send out 8 clocks and the data from the DIN pin will be loaded to SIB at the
rising edge of the CLKI pin. After the 8 clocks have been sent, BUSYI
will be reset to "0" and EVF.5
will be set to "1." At this time, if IEF.5 has been set (IEF.5 = 1), an interrupt is executed; if HEF.5
has been set (HEF.5 = 1), the hold state is terminated. Users can check the status of PSR2.1
(BUSYI) to know whether the serial input process is completed or not. If a serial input process is not
completed, and the SIP R instruction is executed again, the data will be lost. The timing is shown in
Figure 11.
T1
T2
T3
T4
CLKI
(RE3)
Data latch
BUSYI
(PSR2.1)
EVF5
Ins.
DIN
(RE2)
SIP R
1
2
3
4
5
6
7
8
Notes : 1. These clocks at the CLKI pin are internal clock and its frequency is Fosc/2.
2. When the internal signal of the data latch equals to "1,"
then the data in SIB will be loaded into RAM and ACC.
Figure 11. Timing of the Serial Input Function (SIP R)
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