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參數資料
| 型號： | W741E20X |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 4-BIT FLASH MICROCONTROLLER |
| 中文描述： | 4位閃存微控制器 |
| 文件頁數： | 21/84頁 |
| 文件大?。?/td> | 531K |
| 代理商： | W741E20X |
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Preliminary W741E20X
Publication Release Date: March 1998
- 21 -
Revision A1
(2) When the SOP R instruction is executed, the data will be loaded to the serial output buffer (SOB)
and bit 3 of port status register 2 will be set to "1" (BUSYO = 1). Then the CLKO pin will send out 8
clocks and the data in SOB will be sent out at the falling edge of the CLKO pin. After the 8 clocks
have been sent, BUSYO will be reset to "0" and EVF.6 will be set to "1." At this time, if IEF.6 has
been set (IEF.6 = 1), an interrupt is executed; if HEF.6 has been set (HEF.6 = 1), the hold state is
terminated. Users can check the status of PSR2.3 (BUSYO) to know whether the serial output
process is completed or not. If a serial output process is not completed, and the SOP R instruction
is executed again, the data will be lost. The timing is shown in Figure 12.
T1
T2
T3
T4
CLKO
(RE1)
Data latch
BUSYO
(PSR2.3)
EVF6
Ins.
DOUT
(RE0)
SOP R
1
2
3
4
5
6
7
8
Notes : 1. These clocks at the CLKO pin are internal clock and its frequency is Fosc/2.
2. When the internal signal of the data latch equals to "1,"
then the data of the RAM and ACC be loaded to SOB.
Figure 12. Timing of the Serial Output Function (SOP R)
In the above description, the low nibble location of the serial input/output register is contributed to the
ACC, and the high nibble is to R. The port status register 2 (PSR2) including BUSYI,
and BUSYO can
be read out or cleared by the MOVA R, PSR2, or CLR PSR2 instruction.
Port Status Register 2 (PSR2)
Port status register 2 is organized as 4-bit binary register (PSR2.0 to PSR2.3). PSR2 is controlled by
the MOVA R, PSR2, and CLR PSR2
instructions. The bit descriptions are as follows:
Note: R means read only.
R
R
0
1
2
3
PSR2
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