- 您現在的位置：買賣IC網 > PDF目錄363894 > W742C814 (WINBOND ELECTRONICS CORP) 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER PDF資料下載
參數資料
| 型號： | W742C814 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機的小型通用紅外遙控器 |
| 文件頁數： | 13/46頁 |
| 文件大小： | 704K |
| 代理商： | W742C814 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
W742C814
Publication Release Date: February 12, 2003
- 13 -
Revision A2
The organization of the dual-clock operation mode is shown in Figure 6-4.
Oscillator
XIN
XOUT
P L L
Generator
System Clock
Divider 0
Selector
LCD Frequency
T4
T1
T2
T3
HOLD
Fosc
Fslow
Ffast
STOP
enable/disable
SCR.1
Divider 1
SCR.3 (14/12 bit)
Flcd
H CF.4
IN T4
Fslow
Fslow
SCR.0
SCR : System clock Control Register (default = 00h )
Fslow
Bit3
Bit1
Bit0
1 : PLL enable
1 : 12 bit
0 : Fosc = Fslow
1 : Fosc = Ffast
0 : PLL disable
0 : 14 bit
Dual clock operation m ode :
- SCR value will be reset as XX00B after wakeup from STOP m ode
- SCR.0=0, Fosc=Fslow ; SCR.0=1, Fosc=Ffast
- In STOP m ode LCD is turned off
Figure 6-4 Organization of the dual-clock operation mode
6.10 WatchDog Timer (WDT) and WatchDog Timer Register (WDTR)
The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from
unknown errors. When the corresponding option code bit of the WDT set to 1, the WDT is enabled,
and if the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is
F
OSC
/2048. The input clock of the WDT can be switched to F
OSC
/16384 (or F
OSC
/2048) by setting
WDTR.3 to 1. The contents of the WDT can be reset by the instruction CLR WDT. In normal
operation, the application program must reset WDT before it overflows. A WDT overflow indicates that
operation is not under control and the chip will be reset. The WDT overflow period is 1 S when the
sub-system clock (Fslow) is 32 KHz and WDT clock input is Fslow/2048. When the corresponding
option code bit of the WDT set to 0, the WDT function is disabled. The organization of the Divider0
and watchdog timer is shown in Figure 6-5.
相關PDF資料 |
PDF描述 |
|---|---|
| W742E813 | 4-BIT MICROCONTROLLER |
| W742C81A | 4-BIT MICROCONTROLLER |
| W742S819 | 4-BIT TELEPHONE CONTROLLER |
| W742S81A | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| W742S82A | 4-BIT TELEPHONE CONTROLLER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W742C816 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| W742C818 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| W742C81A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4-BIT MICROCONTROLLER |
| W742CE811 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4-BIT MICROCONTROLLER |
| W742E | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4 BIT MICROCONTROLLER |
發布緊急采購，3分鐘左右您將得到回復。