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參數(shù)資料
| 型號(hào)： | W742C814 |
| 廠(chǎng)商： | WINBOND ELECTRONICS CORP |
| 元件分類(lèi)： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機(jī)的小型通用紅外遙控器 |
| 文件頁(yè)數(shù)： | 22/46頁(yè) |
| 文件大小： | 704K |
| 代理商： | W742C814 |
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W742C814
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6.14.1 Hold Mode Release Enable Flag (HEF)
The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The HEF
is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I instruction.
The bit descriptions are as follows:
Note: W means write only.
w
0
1
2
HEF
w
w
w
w
3
4
5
6
7
HEF.0 = 1 Overflow from the Divider 0 causes Hold mode to be released.
HEF.1 = 1 Underflow from Timer 0 causes Hold mode to be released.
HEF.2 = 1 Signal change at port RC causes Hold mode to be released.
HEF.3, HEF.5 & HEF.6 are reserved.
HEF.4 = 1 Overflow from the Divider 1 causes Hold mode to be released.
HEF.7 = 1 Underflow from Timer 1 causes Hold mode to be released.
6.14.2 Interrupt Enable Flag (IEF)
The interrupt enable flag is organized as a 8-bit binary register (IEF.0 to IEF.7). These bits are used to
control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these
interrupts is accepted, the corresponding to the bit of the event flag will be reset, but the other bits are
unaffected. In interrupt subroutine, these interrupts will be disable till the instruction MOV IEF, #I
or EN
INT
is executed again. Otherwise, these interrupts can be disable by executing DIS INT instruction.
The bit descriptions are as follows:
w
1
2
3
IEF
4
w
w
5
6
0
w
w
7
Note: W means write only.
IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0.
IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0.
IEF.2 = 1 Interrupt 2 is accepted by a signal change at port RC.
IEF.3, IEF.5 & IEF.6 are reserved.
IEF.4 = 1 Interrupt 4 is accepted by overflow from the Divider 1.
IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.
6.14.3 Port Enable Flag (PEF)
The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be
used to release the hold mode or preform interrupt function, the content of the PEF must be set first.
The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:
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