
Preliminary W742E81A/W742C81A
Publication Release Date: April 2000
Revision A1
- 23 -
PEF
Note: W means write only.
w
w
w
0
1
2
w
3
PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt.
PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt.
PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt.
PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt.
6.15.4 Hold Mode Release Condition Flag (HCF)
The hold mode release condition flag is organized as a 8-bit binary register (HCF.0 to HCF.7). It
indicates by which interrupt source the hold mode has been released, and is loaded by hardware. The
HCF can be read out by the MOVA R, HCFL
and MOVA R, HCFH instructions. When any of the HCF
bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be reset
by the CLR EVF or MOV HEF,#I (HEF = 0) instructions. When EVF and HEF have been reset, the
corresponding bit of HCF is reset simultaneously. The bit descriptions are as follows:
Note: R means read only.
R
R
HCF
0
1
2
3
4
5
R
R
R
6
7
HCF.0 = 1 Hold mode was released by overflow from the divider 0.
HCF.1 = 1 Hold mode was released by underflow from the timer 0.
HCF.2 = 1 Hold mode was released by a signal change at port RC.
HCF.3 is reserved.
HCF.4 = 1 Hold mode was released by overflow from the divider 1.
HCF.5 = 1 Hold mode was released by underflow from the timer 1.
HCF.6 and HCF.7 are reserved.
6.15.5 Event Flag (EVF)
The event flag is organized as a 8-bit binary register (EVF.0 to EVF.7). It is set by hardware and reset
by CLR EVF,#I instruction or the occurrence of an interrupt. The bit descriptions are as follows:
Note: R means read only.
R
R
R
EVF
0
1
2
3
4
5
R
R
6
7