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參數(shù)資料
| 型號： | W742E813 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT MICROCONTROLLER |
| 中文描述： | 4-BIT, FLASH, 3.58 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 2.75 MM HEIGHT, QFP-100 |
| 文件頁數(shù)： | 25/45頁 |
| 文件大小： | 567K |
| 代理商： | W742E813 |
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Preliminary W742E81A/W742C81A
Publication Release Date: April 2000
Revision A1
- 25 -
6.17 Input/Output Ports RA, RB & RD
Port RA consists of pins RA.0 to RA.3. Port RB consists of pins RB.0 to RB.3. Port RD consists of
pins RD.0 to RD.3. At initial reset, input/output ports RA, RB and RD are all in input mode. When
RA, RB are used as output ports, CMOS or NMOS open drain output type can be selected by the
PM0 register. But when RD is used as output port, the output type is just fixed to be CMOS output
type. Each pin of port RA, RB and RD can be specified as input or output mode independently by the
PM1, PM2 and PM5 registers. The MOVA R, RA or MOVA R, RB or MOVA R, RD instructions
operate the input functions and the MOV RA, R or MOV RB, R or MOV RD, R operate the output
functions. For more details, refer to the instruction table and Figure 6-10 and Figure 6-11.
Input/Output Pin of the RA(RB)
I/O PIN
RA.n(RB.n)
DATA
BUS
Buffer
Output
PM0.0(PM0.1)
PM1.n (PM2.n)
MOVA R,RA(MOVA R,RB) instruction
MOV RA,R(MOV RB,R)
instruction
Enable
Enable
Figure 6-10 Architecture of RA (RB) Input/Output Pins
Input/Output Pin of the RD
I/O PIN
RD.n
DATA
BUS
Buffer
Output
PM5.n
MOVA R,RD instruction
MOV RD,R instruction
Enable
Enable
Figure 6-11 Architecture of RD Input/Output pins
6.17.1 Port Mode 0 Register (PM0)
The port mode 0 register is organized as 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to
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